System and method for reducing latency in a floating point processor

Claim 1

In a floating point processor having a carry propagate adder, an improvement for enhancing performance by reducing latency comprising a rounding means connected to said carry propagate adder, said rounding means and said carry propagate adder for receiving first, second, third and fourth inputs, said rounding means for performing a rounding operation using the first and second inputs approximately simultaneously when an addition operation is performed on the third and fourth inputs by said carry propagate adder, said rounding means for providing a rounded output, said rounding means including: a carry select adder for adding the first and second inputs to generate a first preliminary result, and for generating second and third preliminary results by adding a logic "1" and a logic "0" to the first preliminary result; a rounding logic network communicating with said carry propagate adder and said carry select adder, generating an input carry select signal to select one of the second and third preliminary results; and said carry select adder and said rounding logic network for jointly providing the rounded output, based on the selected one of the second and third preliminary results.

Claim 8

A system receiving first, second, third and fourth inputs, for reducing latency in a floating point processor, the system comprising: a carry propagate adder for receiving the third and fourth inputs and for performing an addition function on the third and fourth inputs; and a rounding means connected to said carry propagate adder, said rounding means for receiving the first and second inputs and for performing a rounding function approximately concurrently with said addition function and for providing a rounded output. said rounding means including: a carry select adder generating second and third preliminary results by adding a logic "1" and a logic "0", respectively, to the first preliminary result; a rounding logic network communicating with said carry propagate adder and said carry select adder, generating a carry select input signal to select one of the second and third preliminary results; and said carry select adder and said rounding logic network for jointly providing said rounded output, based on the selected one of the second and third preliminary results.

Claim 9

A system receiving first, second, third and fourth inputs, for reducing latency in a floating point processor, the system comprising: a carry propagate adder for receiving the third and fourth inputs and for performing an addition function on the third and fourth inputs; and a rounding means connected to said carry propagate adder, said rounding means for receiving the first and second inputs and for performing a rounding function approximately concurrently with said addition function and for providing a rounded output. said rounding means including: a carry select adder generating second and third preliminary results by adding a logic "1" and a logic "0", respectively, to the first preliminary result; a rounding logic network communicating with said carry propagate adder and said carry select adder, generating a carry select input signal to select one of the second and third preliminary results; and said carry select adder and said rounding logic network for jointly providing said rounded output, based on the selected one of the second and third preliminary results.

Claim 12

A system for reducing latency in a floating point processor, comprising: a carry propagate adder for receiving inputs and for performing an addition function on the inputs; and a rounding means connected to said carry propagate adder, said rounding means for receiving the inputs and for performing a rounding function approximately concurrently with said addition function and for providing a rounded output. said rounding means including: a carry select adder, and a rounding logic network communicating with said carry propagate adder and said carry select adder; and said carry select adder and said rounding logic network for jointly providing said rounded output; a normalizer for normalizing said rounded output subsequent to said rounding operation in order to derive a post-normalized output; and a logic means for selectively forcing said post-normalized output to an even number when said rounded output has a lost precision equal to 1/2 of a least significant bit, said logic means including an inverter for inverting a least significant bit of said rounded output to derive an inverter output, and a logic gate for performing an AND logic operation, said logic gate for combining said inverter output with a least significant bit of said post-normalized output to derive an ultimate least significant bit of said post-normalized output.

Claim 13

A system for reducing latency in a floating point processor, comprising: a carry propagate adder for receiving inputs and for performing an addition function on the inputs; and a rounding means connected to said carry propagate adder, said rounding means for receiving the inputs and for performing a rounding function approximately concurrently with said addition function and for providing a rounded output. said rounding means including: a carry select adder, and a rounding logic network communicating with said carry propagate adder and said carry select adder; and said carry select adder and said rounding logic network for jointly providing said rounded output; a normalizer for normalizing said rounded output subsequent to said rounding operation in order to derive a post-normalized output; and a logic means for selectively forcing said post-normalized output to an even number when said rounded output has a lost precision equal to 1/2 of a least significant bit, said logic means including an inverter for inverting a least significant bit of said rounded output to derive an inverter output, and a logic gate for performing an AND logic operation, said logic gate for combining said inverter output with a least significant bit of said post-normalized output to derive an ultimate least significant bit of said post-normalized output.

Claim 14

A method for enhancing performance in a floating point processor by reducing latency, the method using first, second, third and fourth inputs, the method comprising the steps of: performing addition on the third and fourth inputs using carry propagation to derive an addition result; rounding said addition result to derive a first part of a rounded output and a carry select input signal indicative of whether said rounding generates a carry, performing addition on the first and second inputs more significant than the third and fourth inputs, respectively, to generate a first preliminary result, said addition on the first and second inputs being performed approximately simultaneously with said step of rounding, adding a logic "1" and a logic "0" to the first preliminary result, to generate second and third preliminary results, respectively; selecting one of the second and third preliminary results, based on the carry select input signal; and outputting the selected one of the second and third preliminary results as a second part of the rounded output.

Claim 15

A method for enhancing performance in a floating point processor by reducing latency, the method using first, second, third and fourth inputs, the method comprising the steps of: performing addition on the third and fourth inputs using carry propagation to derive an addition result; rounding said addition result to derive a first part of a rounded output and a carry select input signal indicative of whether said rounding generates a carry, performing addition on the first and second inputs more significant than the third and fourth inputs, respectively, to generate a first preliminary result, said addition on the first and second inputs being performed approximately simultaneously with said step of rounding, adding a logic "1" and a logic "0" to the first preliminary result, to generate second and third preliminary results, respectively; selecting one of the second and third preliminary results, based on the carry select input signal; and outputting the selected one of the second and third preliminary results as a second part of the rounded output.

Claim 17

A method for enhancing performance in a floating point processor by reducing latency, the method comprising the steps of: performing addition on inputs using carry propagation to derive a result, the result including successive bits of lost precision, said successive bits including first, second and third bits in order of significance; rounding said result approximately simultaneously with said addition to derive a rounded output; performing a round-to-nearest rounding process to derive a rounded result from said result; rounding up if said first bit exhibits a logic high; rounding down if said first bit exhibits a logic low; normalizing said rounded result to derive a post-normalized result; and after normalization, forcing said post-normalized result to even, if prior to said normalization said first bit exhibited a logic high and both said second and third bits exhibited a logic low.

Claim 18

A method for enhancing performance in a floating point processor by reducing latency, the method comprising the steps of: performing addition on inputs using carry propagation to derive a result, the result including successive bits of lost precision, said successive bits including first, second and third bits in order of significance; rounding said result approximately simultaneously with said addition to derive a rounded output; performing a round-to-nearest rounding process to derive a rounded result from said result; rounding up if said first bit exhibits a logic high; rounding down if said first bit exhibits a logic low; normalizing said rounded result to derive a post-normalized result; and after normalization, forcing said post-normalized result to even, if prior to said normalization said first bit exhibited a logic high and both said second and third bits exhibited a logic low.

Claim 22

An apparatus receiving first and second mantissa data, the apparatus comprising: a carry propagate adder including a first arithmetic logic unit, coupled to receive least significant parts of the first and second mantissa data, to arithmetically operate on the least significant parts of the first and second mantissa data with the first arithmetic logic unit, to generate an output including a carry output from the least significant bit; a rounding logic network coupled to receive a part of the output of the carry propagate adder, including a combinational logic circuit to generate a least significant part of a rounded output and a carry select input signal indicative of whether the rounding logic network generates a carry in generating the least significant part of the rounded output; and a carry select adder including a second arithmetic logic unit, coupled to receive the most significant parts of the first and second mantissa data, coupled to the carry propagate adder to receive the carry output from the least significant bit, and coupled to the rounding logic network to receive the carry select input signal, generating a first preliminary result using the second arithmetic logic unit, based on the most significant parts of the first and second mantissa data and the carry output from the least significant bit, adding a logic "0" and a logic "1" to the first preliminary result to generate second and third preliminary results, and for outputting one of the second and third preliminary results as a most significant part of the rounded output, based on the carry select input signal.

Claim 23

An apparatus receiving first and second mantissa data, the apparatus comprising: a carry propagate adder including a first arithmetic logic unit, coupled to receive least significant parts of the first and second mantissa data, to arithmetically operate on the least significant parts of the first and second mantissa data with the first arithmetic logic unit, to generate an output including a carry output from the least significant bit; a rounding logic network coupled to receive a part of the output of the carry propagate adder, including a combinational logic circuit to generate a least significant part of a rounded output and a carry select input signal indicative of whether the rounding logic network generates a carry in generating the least significant part of the rounded output; and a carry select adder including a second arithmetic logic unit, coupled to receive the most significant parts of the first and second mantissa data, coupled to the carry propagate adder to receive the carry output from the least significant bit, and coupled to the rounding logic network to receive the carry select input signal, generating a first preliminary result using the second arithmetic logic unit, based on the most significant parts of the first and second mantissa data and the carry output from the least significant bit, adding a logic "0" and a logic "1" to the first preliminary result to generate second and third preliminary results, and for outputting one of the second and third preliminary results as a most significant part of the rounded output, based on the carry select input signal.