US5388230A
Expired / Lapsed
US
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Parallel processor having multi-processing units either connected or bypassed in either series or parallel by the use of bus switching
Assignee: Renesas Electronics Corp
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Filing: 1993-08-12
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Granted: 1995-02-07
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Expires: 2013-08-12
Abstract
Abstract A parallel process which includes a plurality of processing units connected to each other via input/output ports. Each of the plurality of processing units includes a memory for storing a program and data, a local bus for inputting/outputting the program and data to and from the memory having an address signal line, a data signal line, and a control signal line, a CPU for reading the program from the memory via the local bus, reading data needed to execute the program from the memory via the local bus, and storing data which has been updated due to the execution of the program in the memory via the local bus, and a plurality of input/output ports for connecting the local bus to a plurality of outside buses. The input/output ports are used by the CPU to input/output data to and from an outside memory connected to an outside bus or by an outside CPU, connected to an outside bus, to input/output data to and from the memory. At least one bypass switch is provided for controllably connecting two of the outside buses to permit data transference between the outside CPU and the outside memory thereby bypassing the CPU and the memory. Also provided is a main CPU for setting program and data in the processing units and recovering data from the processing units.
Inventors
- 👤 Hiromichi Yamada
- 👤 Koyo Katsura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:54
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
377 words
A parallel processor comprising a plurality of processing units connected to each other via input/output ports and a main CPU connected to at least one of said processing units to control said processing units, wherein each processing unit comprises: a CPU, a memory for storing data and programs to be executed by said CPU, a local bus connected to said CPU and said memory, a plurality of input/output ports, having a corresponding number of outside terminals, connected to said local bus within each of said processing units, said outside terminals being connected to outside buses external of each of said processing units, and a bus switch for mutually connecting a pair of said outside terminals connected to a pair of said input/output ports, said pair of said input/output ports being a selected two of said plurality of input/output ports; wherein at least one of said processing units having one of said outside terminals connected to one of the input/output ports has said at least one of said outside terminals connected via an outside bus to an input/output port of said main CPU, and the rest of said outside terminals of said at least one of said processing units are connected via outside buses to a corresponding number of said processing units such that there is at least a pair of said processing units connected in series; wherein a selected pair of said outside terminals of said each of said processing units is connected to each other via said bus switch for bypassing said each of said processing units; wherein said main CPU, having a function to modify an inter-relationship of connections between said plurality of processing units, controls said bus switch of any one of said processing units by opening and closing said bus switch to disconnect and connect, respectively, said outside buses of both sides of said bus switch via said bus switch, whereby any one of said processing units can be bypassed; and wherein said CPU of said each of said processing units reads said programs from said memory and processes according to a demand of said programs to access data of said memory and data of said memory within another processing unit connected in series or parallel with said each of said processing units.
Claim 2
Dependent Claim
377 words
A parallel processor comprising a plurality of processing units connected to each other via input/output ports and a main CPU connected to at least one of said processing units to control said processing units, wherein each processing unit comprises: a CPU, a memory for storing data and programs to be executed by said CPU, a local bus connected to said CPU and said memory, a plurality of input/output ports, having a corresponding number of outside terminals, connected to said local bus within each of said processing units, said outside terminals being connected to outside buses external of each of said processing units, and a bus switch for mutually connecting a pair of said outside terminals connected to a pair of said input/output ports, said pair of said input/output ports being a selected two of said plurality of input/output ports; wherein at least one of said processing units having one of said outside terminals connected to one of the input/output ports has said at least one of said outside terminals connected via an outside bus to an input/output port of said main CPU, and the rest of said outside terminals of said at least one of said processing units are connected via outside buses to a corresponding number of said processing units such that there is at least a pair of said processing units connected in series; wherein a selected pair of said outside terminals of said each of said processing units is connected to each other via said bus switch for bypassing said each of said processing units; wherein said main CPU, having a function to modify an inter-relationship of connections between said plurality of processing units, controls said bus switch of any one of said processing units by opening and closing said bus switch to disconnect and connect, respectively, said outside buses of both sides of said bus switch via said bus switch, whereby any one of said processing units can be bypassed; and wherein said CPU of said each of said processing units reads said programs from said memory and processes according to a demand of said programs to access data of said memory and data of said memory within another processing unit connected in series or parallel with said each of said processing units.
Claim 3
Dependent Claim
46 words
A parallel processor according to claim 1, wherein said bus switch of each of said processing unit is provided with a register, and whether said bus switch should be opened/closed is determined by comparing information stored in said register with information supplied from said main CPU.
Claim 4
Dependent Claim
35 words
A parallel processor according to claim 2, wherein said register is so arranged that information stored therein can be rewritten on the basis of information supplied from said CPU in said processing unit belonging thereto.
Claim 5
Dependent Claim
118 words
A parallel processor according to claim 1, wherein said memory of each of said processing units is provided with a message region distinguished from a region storing said program and data in accordance with an address, to temporarily store a message supplied from outside of each of said processing units in said message region, each of said processing units is provided with a register for storing a front address and a number of said message stored in said message region, and said CPU of each of said processing units refers to said register at a constant time interval to read out and process said message from said message region if said message is stored in said message region.
Claim 6
Dependent Claim
76 words
A parallel processor according to claim 4, wherein in case of transferring a plurality of data constituting said message to said message region of said processing units connected in series or parallel, after transferring said front address of said plurality of data, said CPU of each of said processing units discards addresses of data after the second address of data and successively transfers said plurality of data including both a data bus and an address bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |