Patent US5388067A successfully refreshed from Google Patents.
US5388067A
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Semiconductor memory cell
Assignee: NEC Corp
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Filing: 1994-04-01
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Granted: 1995-02-07
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Expires: 2014-04-01
Abstract
Abstract A flip-flop is composed of inverters including first and second MISFETs each comprising a TFT or an SOI transistor. A third MISFET, which comprises a TFT or an SOI transistor, has a gate connected to a write selecting signal line, and is connected between the output terminal of one of the inverters and a write/read signal line. A fourth MISFET has a gate connected to the gate of the other inverter. A fifth MISFET has a drain and a source connected to the write/read signal line and the drain of the fourth MISFET, and a gate connected to a read selecting signal line.
Inventors
- 👤 Nolifumi Sato
- 👤 Manabu Ando
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:15
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10B10/15; H10D; H10D86/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
207 words
A semiconductor memory cell comprising: a flip-flop having a first inverter composed of a first MISFET and a first load element and a second inverter composed of a second MISFET and a second load element, said first and second inverters having respective input terminals connected to the respective output terminals of the second and first inverters; a third MISFET having a source and a drain, one of which is connected to the output terminal of said first or second inverter; a fourth MISFET having a gate connected to the output terminal of said second or first inverter; a fifth MISFET having a drain and a source connected to the other of the source and drain of said third MISFET and the drain of said fourth MISFET, respectively; fixed potential supply means for supplying a fixed potential to the source of said fourth MISFET; a read selecting signal line connected to the gate of said fifth MISFET; a write selecting signal line connected to the gate of said third MISFET; and a first write/read signal line connected to the other of the source and drain of said third MISFET; each of said first MISFET, said second MISFET, and said third MISFET being a TFT or an SOI transistor.
Claim 2
Dependent Claim
207 words
A semiconductor memory cell comprising: a flip-flop having a first inverter composed of a first MISFET and a first load element and a second inverter composed of a second MISFET and a second load element, said first and second inverters having respective input terminals connected to the respective output terminals of the second and first inverters; a third MISFET having a source and a drain, one of which is connected to the output terminal of said first or second inverter; a fourth MISFET having a gate connected to the output terminal of said second or first inverter; a fifth MISFET having a drain and a source connected to the other of the source and drain of said third MISFET and the drain of said fourth MISFET, respectively; fixed potential supply means for supplying a fixed potential to the source of said fourth MISFET; a read selecting signal line connected to the gate of said fifth MISFET; a write selecting signal line connected to the gate of said third MISFET; and a first write/read signal line connected to the other of the source and drain of said third MISFET; each of said first MISFET, said second MISFET, and said third MISFET being a TFT or an SOI transistor.
Claim 3
Dependent Claim
73 words
A semiconductor memory cell according to claim 1, further comprising: a sixth MISFET having a source and a drain, one of which is connected to an output terminal of said second or first inverter, and a gate connected to said write selecting signal line; and a second write/read signal line connected to the other of the source and drain of said sixth MISFET, said sixth MISFET being a TFT or an SOI transistor.
Claim 4
Dependent Claim
80 words
A semiconductor memory cell according to claim 2, further comprising: a seventh MISFET having a gate and a source which are connected to the output terminal of said first or second inverter and fixed potential supply means, respectively; and an eighth MISFET having a source and a drain, one of which is connected to the drain of said seventh MISFET and the other connected to said second write/read signal line, and a gate connected to said read selecting signal line.
Claim 5
Dependent Claim
34 words
A semiconductor memory cell according to claim 1, wherein a film serving as the gate of each of said first, second, and third MISFETs is disposed below a film serving as the channel thereof.
Claim 6
Dependent Claim
34 words
A semiconductor memory cell according to claim 2, wherein a film serving as the gate of each of said first, second, and third MISFETs is disposed below a film serving as the channel thereof.
Claim 7
Dependent Claim
34 words
A semiconductor memory cell according to claim 3, wherein a film serving as the gate of each of said first, second, and third MISFETs is disposed below a film serving as the channel thereof.
Claim 8
Dependent Claim
34 words
A semiconductor memory cell according to claim 1, wherein a film serving as the gate of each of said first, second, and third MISFETs is disposed above a film serving as the channel thereof.
Claim 9
Dependent Claim
34 words
A semiconductor memory cell according to claim 2, wherein a film serving as the gate of each of said first, second, and third MISFETs is disposed above a film serving as the channel thereof.
Claim 10
Dependent Claim
34 words
A semiconductor memory cell according to claim 3, wherein a film serving as the gate of each of said first, second, and third MISFETs is disposed above a film serving as the channel thereof.
Claim 11
Dependent Claim
26 words
A semiconductor memory cell according to claim 1, wherein each of said first, second, and third MISFETs has gates disposed above and below the channel thereof.
Claim 12
Dependent Claim
26 words
A semiconductor memory cell according to claim 2, wherein each of said first, second, and third MISFETs has gates disposed above and below the channel thereof.
Claim 13
Dependent Claim
26 words
A semiconductor memory cell according to claim 3, wherein each of said first, second, and third MISFETs has gates disposed above and below the channel thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |