Dual port static RAM with bidirectional shift capability

Claim 2

An integrated circuit memory, comprising: first and second pluralities of bitline pairs; an array of dual storage cells; each dual storage cell of said array of dual storage cells comprising a first latch connected between a first pair of data nodes and a second latch connected between a second pair of data nodes; and each dual storage cell of said array of dual storage cells further comprising a first pair of pass transistors connected to said first pair of data nodes and a second pair of pass transistors connected to said second pair of data nodes; said first pair of pass transistors of each dual storage cell of said array of dual storage cells connected to one pair of said first plurality of bitline pairs, and said second pair of pass transistors of each dual storage cell of said array of dual storage cells connected to one pair of said second plurality of bitline pairs; each dual storage cell of said array of dual storage cells connected to receive first and second control signals; and each dual storage cell of said array of dual storage cells further comprising a transfer circuit wherein, for each dual storage cell of said array of dual storage cells, the transfer circuit is coupled to said first and second pairs of data nodes and configured to drive one data node of said second pair of data nodes when said first control signal is activated, which data node driven determined in accordance with logic levels of said first pair of data nodes and to drive one data node of said first pair of data nodes when said second control signal is activated, which data node of said first pair of data nodes driven determined in accordance with logic levels of said first pair of data nodes.

Claim 3

The memory of claim 1, wherein each latch is a CMOS latch; and wherein each first pair of data nodes has a first node and a second node and each second pair of data nodes has a first node and a second node; and wherein, for each dual storage cell of said array of dual storage cells, the transfer circuit includes a first pair of NMOS transistors connected in series between said first node of said first pair of data nodes and ground, said first pair of NMOS transistors configured to drive said first node of said first pair of data nodes toward ground if said first node of said second pair of data nodes is high and said first control signal is high; a second pair of NMOS transistors connected in series between said second node of said first pair of data nodes and ground, said second pair of NMOS transistors configured to drive said second node of said first pair of data nodes toward ground if said second node of said second pair of data nodes is high and said first control signal is high; a third pair of NMOS transistors connected in series between said first node of said second pair of data nodes and ground, said third pair of NMOS transistors configured to drive said first node of said second pair of data nodes toward ground if said first node of said first pair of data nodes is high and said second control signal is high; and a fourth pair of NMOS transistors connected in series between said second node of said second pair of data nodes and ground, said fourth pair of NMOS transistors configured to drive said second node of said second of said second pair of data nodes toward ground if said second node of said first pair of data nodes is high and said second control signal is high.

Claim 4

The memory of claim 1, wherein, for each of dual storage cells of said array of dual storage cells, said first and second latches are CMOS static latches.