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Patent US5387825A successfully refreshed from Google Patents.
US5387825A
Expired / Lapsed
US
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Glitch-eliminator circuit
Assignee: Texas Instruments Inc
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Filing: 1992-08-20
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Granted: 1995-02-07
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Expires: 2012-08-20
Abstract
Abstract One embodiment of the present invention is a digital circuit (10) for providing glitch-free data in an asynchronous environment, the circuit comprising: an input circuit (11) for accepting data; combinational logic circuitry (12) for accepting the data from the input circuit (11 ) and manipulating the data to provide output data, wherein a delay in data flow occurs while the combinational logic manipulates the data; and an output circuit (14) for accepting the output data at a predetermined period after the receipt of data by the input circuit. Preferably, the predetermined period is at least as long as the delay in data flow.
Inventors
- 👤 Jay T. Cantrell
- 👤 Edward R. Schurig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
164 words
A digital circuit for providing a glitch-free output in an asynchronous environment, said circuit comprising: pulse forming circuitry for creating an asynchronous pulse, said asynchronous pulse having a first edge, a second edge, and a finite duration between said first and said second edges; an input circuit for accepting input data based on the receipt of the first edge of the asynchronous pulse; combinational logic circuitry for accepting data from said input circuit and manipulating said data from said input circuit to provide output data, wherein the outputting of data is delayed while said combinational logic circuitry manipulates said data from said input circuit; and an output circuit for blocking said data output by said combinational logic circuitry during said finite duration of said asynchronous pulse; wherein said finite duration of said asynchronous pulse is at least as long as said delay of outputting said data by said combinational logic circuitry and said input data is not directly received by said combinational logic circuitry.
Claim 2
Dependent Claim
164 words
A digital circuit for providing a glitch-free output in an asynchronous environment, said circuit comprising: pulse forming circuitry for creating an asynchronous pulse, said asynchronous pulse having a first edge, a second edge, and a finite duration between said first and said second edges; an input circuit for accepting input data based on the receipt of the first edge of the asynchronous pulse; combinational logic circuitry for accepting data from said input circuit and manipulating said data from said input circuit to provide output data, wherein the outputting of data is delayed while said combinational logic circuitry manipulates said data from said input circuit; and an output circuit for blocking said data output by said combinational logic circuitry during said finite duration of said asynchronous pulse; wherein said finite duration of said asynchronous pulse is at least as long as said delay of outputting said data by said combinational logic circuitry and said input data is not directly received by said combinational logic circuitry.
Claim 3
Dependent Claim
14 words
The digital circuitry of claim 1 wherein said input circuit is a D flip-flop.
Claim 4
Dependent Claim
14 words
The digital circuitry of claim 1 wherein said output circuit is a D latch.
Claim 5
Dependent Claim
20 words
The digital circuit of claim 1 wherein said pulse forming circuitry includes: an AND gate and an inverting delay element.
Claim 6
Dependent Claim
22 words
The digital circuit of claim 1, wherein said pulse forming circuitry includes: a NAND gate, an inverter, and an inverting delay element.
Claim 7
Dependent Claim
142 words
A digital circuit for providing glitch-free data in an asynchronous environment, said digital circuit comprising: an input circuit for accepting input data upon receipt of an edge of an asynchronous signal, said asynchronous signal having an edge; combinational logic circuitry for accepting said data from said input circuit and manipulating said data from said input circuit to provide output data, wherein a delay in data flow occurs while said combinational logic circuitry manipulates said data from said input circuit; a delay circuit for delaying said asynchronous signal for a period at least as long as said delay of data flow, and wherein said delayed asynchronous signal has a delayed edge; and an output circuit for accepting said output data upon the receipt of a delayed edge of said delayed asynchronous pulse; wherein said combinational logic circuitry receives exclusively from said input circuitry.
Claim 8
Dependent Claim
142 words
A digital circuit for providing glitch-free data in an asynchronous environment, said digital circuit comprising: an input circuit for accepting input data upon receipt of an edge of an asynchronous signal, said asynchronous signal having an edge; combinational logic circuitry for accepting said data from said input circuit and manipulating said data from said input circuit to provide output data, wherein a delay in data flow occurs while said combinational logic circuitry manipulates said data from said input circuit; a delay circuit for delaying said asynchronous signal for a period at least as long as said delay of data flow, and wherein said delayed asynchronous signal has a delayed edge; and an output circuit for accepting said output data upon the receipt of a delayed edge of said delayed asynchronous pulse; wherein said combinational logic circuitry receives exclusively from said input circuitry.
Claim 9
Dependent Claim
14 words
The digital circuit of claim 6 wherein said input circuit is a D flip-flop.
Claim 10
Dependent Claim
14 words
The digital circuit of claim 6 wherein said output circuit is a D flip-flop.
Claim 11
Dependent Claim
152 words
A digital circuit for providing a glitch-free output in an asynchronous environment, said circuit comprising: pulse forming circuitry for creating an asynchronous pulse, said asynchronous pulse having a first edge, a second edge, and a finite duration between said first and said second edges; an input circuit for accepting input data based on the receipt of the first edge of the asynchronous pulse; combinational logic circuitry for accepting data exclusively from said input circuit and manipulating said data from said input circuit to provide output data, wherein the outputting of data is delayed while said combinational logic circuitry manipulates said data from said input circuit; and an output circuit for retaining said data output by said combinational logic circuitry during said finite duration of said asynchronous pulse; wherein said finite duration of said asynchronous pulse is at least as long as said delay of outputting said data by said combinational logic circuitry.
Claim 12
Dependent Claim
152 words
A digital circuit for providing a glitch-free output in an asynchronous environment, said circuit comprising: pulse forming circuitry for creating an asynchronous pulse, said asynchronous pulse having a first edge, a second edge, and a finite duration between said first and said second edges; an input circuit for accepting input data based on the receipt of the first edge of the asynchronous pulse; combinational logic circuitry for accepting data exclusively from said input circuit and manipulating said data from said input circuit to provide output data, wherein the outputting of data is delayed while said combinational logic circuitry manipulates said data from said input circuit; and an output circuit for retaining said data output by said combinational logic circuitry during said finite duration of said asynchronous pulse; wherein said finite duration of said asynchronous pulse is at least as long as said delay of outputting said data by said combinational logic circuitry.
Claim 13
Dependent Claim
161 words
A digital circuit for providing a glitch-free output in an asynchronous environment, said circuit comprising: pulse forming circuitry for creating an asynchronous pulse, said asynchronous pulse having a first edge, a second edge, and a finite duration between said first and said second edges; an input circuit for accepting input data based on the receipt of the first edge of the asynchronous pulse, said input data is exclusively received by said input circuit; combinational logic circuitry for accepting data from said input circuit and manipulating said data from said input circuit to provide output data, wherein the outputting of data is delayed while said combinational logic circuitry manipulates said data from said input circuit; and an output circuit for retaining said data output by said combinational logic circuitry during said finite duration of said asynchronous pulse; wherein said finite duration of said asynchronous pulse is at least as long as said delay of outputting said data by said combinational logic circuitry.
Claim 14
Dependent Claim
161 words
A digital circuit for providing a glitch-free output in an asynchronous environment, said circuit comprising: pulse forming circuitry for creating an asynchronous pulse, said asynchronous pulse having a first edge, a second edge, and a finite duration between said first and said second edges; an input circuit for accepting input data based on the receipt of the first edge of the asynchronous pulse, said input data is exclusively received by said input circuit; combinational logic circuitry for accepting data from said input circuit and manipulating said data from said input circuit to provide output data, wherein the outputting of data is delayed while said combinational logic circuitry manipulates said data from said input circuit; and an output circuit for retaining said data output by said combinational logic circuitry during said finite duration of said asynchronous pulse; wherein said finite duration of said asynchronous pulse is at least as long as said delay of outputting said data by said combinational logic circuitry.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |