US5387530A
Expired / Lapsed
US
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Threshold optimization for soi transistors through use of negative charge in the gate oxide
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-06-29
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Granted: 1995-02-07
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Expires: 2013-06-29
Abstract
Abstract Threshold optimization for SOI transistors is achieved through the formation of a layer of charge within the gate oxide, which layer has a polarity corresponding to that of the ion implantation for threshold voltage control. A negative charge layer is formed by furnishing trace amounts of aluminum on the substrate before growth of an oxide to form a portion of the gate oxide. The aluminum will form a charge layer on the surface of the oxide and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the charge layer in the same.
Inventors
- 👤 Brian S. Doyle
- 👤 Ara Philipossian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:10
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/65; H10P14/6502; H10P14/6508; H10P70/00; H10P70/10; H10P70/15; H10D64/01346; Y; Y10; Y10S; Y10S438/00; Y10S438/91
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
93 words
A method, comprising the steps of: forming a silicon-on-insulator (SOI) substrate having an active region thickness of approximately 1000 angstroms; forming on said SOI substrate a gate insulator layer having a thickness of approximately 65 angstroms and including an inner layer located in approximately the middle thereof and having an areal density of negative charge of approximately 1.5×10 12 electrons per square centimeter; and doping the region of said substrate beneath said gate insulator layer with an n-type dopant to a volumetric dopant density of approximately 5×10 16 dopant atoms per cubic centimeter.
Claim 2
Independent Claim
93 words
A method, comprising the steps of: forming a silicon-on-insulator (SOI) substrate having an active region thickness of approximately 1000 angstroms; forming on said SOI substrate a gate insulator layer having a thickness of approximately 65 angstroms and including an inner layer located in approximately the middle thereof and having an areal density of negative charge of approximately 1.5×10 12 electrons per square centimeter; and doping the region of said substrate beneath said gate insulator layer with an n-type dopant to a volumetric dopant density of approximately 5×10 16 dopant atoms per cubic centimeter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |