US3624466A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Depletion-type igfet having high-conductivity n-type channel
Assignee: Arris Technology Inc
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Filing: 1970-03-02
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Granted: 1971-11-30
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Expires: 1990-03-02
Abstract
Abstract A depletion-type insulated gate field effect transistor (IGFET) comprising (1) a P-type semiconductive wafer containing N-type source and drain regions, and a relatively low resistivity N-type region at the surface of said wafer which provides a conductive channel between said source and drain regions, (2) an oxide insulating layer overlying said wafer, and (3) a conductive gate electrode overlying the part of said insulating layer which overlies said conductive channel. During its fabrication, the IGFET is heat treated by baking it at at least 500* C. for about several hours or longer; this provides in said oxide layer a sufficient density of positive charges to induce more than about 5 X 1011 electrons per square centimeter at the surface of the wafer between the source and drain regions, thereby to create said N-type region at the surface of said wafer.
Inventors
- 👤 George L Schnable
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:40
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10D; H10D99/00; H10P14/6322
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
43 words
The transistor of claim 1 wherein one of said source and drain regions substantially surrounds the other of said source and drain regions and said gate electrode overlies a part only of the portion of said wafer between said source and drain regions.
Claim 2
Dependent Claim
55 words
The transistor of claim 1 wherein the portion of said wafer between the opposing edges of said source and drain regions is elongated, said gate electrode is elongated and narrower than said portion of said wafer between said source and drain regions, and said gate electrode surrounds completely one of said source and drain regions.
Claim 3
Dependent Claim
32 words
The transistor of claim 1 further including two separate metallic contacts, each extending through a respective opening in said oxide layer, one to said source regions and one to said drain region.
Claim 4
Dependent Claim
158 words
A process for forming a depletion-type insulated gate field effect transistor in a monocrystalline wafer of P-conductivity type having a surface, comprising: diffusing spaced-apart N-conductivity-type source and drain regions, respectively, into said surface of said wafer, forming over at least the portion of said surface of said wafer between said source and drain regions a layer of an oxide of said semiconductive material, baking said oxide layer at a temperature of at least about 500* C. for a sufficient time to provide in said oxide layer a sufficient density of positive charges for inducing more than 5 X 1011 electrons per square centimeter at said surface of said wafer, thereby providing a correspondingly lower resistivity N-type inversion layer at the portion of said surface of said wafer between said source and drain regions, and forming a gate electrode comprising a conductive layer overlying said oxide layer and the portion of said wafer between said source and drain regions.
Claim 5
Dependent Claim
27 words
The process of claim 5 wherein said baking is performed in an atmosphere of dry nitrogen at a temperature of about 1,200* C. for about 15 hours.
Claim 6
Dependent Claim
18 words
The process of claim 5 wherein said baking is performed in an atmosphere for nitrogen for 2 hours.
Claim 7
Dependent Claim
26 words
The process of claim 5 wherein said baking is performed in normal air having a 50 percent relative humidity at a reference temperature of 25* C.
Claim 8
Dependent Claim
48 words
The process of claim 5 wherein said oxide layer is formed over said surface of said wafer including said source and drain regions, said process including the additional step of forming separate metallic contacts to said source and drain regions, respectively, through respective openings in said oxide layer.
Claim 9
Dependent Claim
64 words
The process of claim 5 wherein said source and drain regions are shaped and aligned such that an elongated portion Of said wafer separates the opposing edges of said source and drain regions and said gate electrode is elongated and aligned with said elongated portion of said wafer between said source and drain regions and is narrower than said elongated portion of said wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-29 | 1975-05-31 | 1975-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-29 | 1979-05-31 | 1979-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-29 | 1983-05-31 | 1983-11-30 | $7700.00 | Window Closed / Lapsed |