US5386383A
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Method and apparatus for controlling dynamic random access memory devices
Assignee: AT&T Inc
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Filing: 1994-02-28
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Granted: 1995-01-31
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Expires: 2014-02-28
Abstract
Abstract A memory system (30), comprised of a plurality of banks (320-327) of DRAM devices (10) is controlled by a memory controller (34) that not only determines the presence and density of the DRAM devices upon power-up, but also controls their addressing during normal operation. The memory controller addresses the DRAM devices in each bank by providing each with a complete row address and a complete column address that simultaneously specifies the row and column address for the condition when the DRAM device is symmetric and asymmetric. In this way, the controller can accommodate both symmetric and asymmetric DRAM devices in the same bank.
Inventors
- 👤 Partha Raghavachari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
293 words
A method for controlling a plurality of banks of DRAM devices, each DRAM device comprised of a plurality of memory cells arrayed in rows and columns, each cell being uniquely identified by a row address and a column address, the method comprising the steps of: decoding an incoming address, specifying a cell of interest in each DRAM device in a bank, to designate the bank of DRAM devices each containing the cell of interest; multiplexing the incoming address to generate a complete row address that specifies the row in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and simultaneously specifies the row containing the cell of interest row when the DRAM device has an unequal number of rows and columns; multiplexing the incoming address to generate a complete column address that specifies the column in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and that simultaneously specifies the row containing the cell of interest row when the DRAM device has an unequal number of rows and columns; sequentially applying the complete row address and the complete column address to each DRAM device in the designated bank; decoding only as much of the complete row address at each DRAM device as is necessary, in accordance with the number and columns in the DRAM device, to select the row containing the cell of interest; and decoding only as much of the complete column address at each DRAM device as is necessary, in accordance with the number and columns in the DRAM device, to select the row containing the cell of interest.
Claim 2
Independent Claim
293 words
A method for controlling a plurality of banks of DRAM devices, each DRAM device comprised of a plurality of memory cells arrayed in rows and columns, each cell being uniquely identified by a row address and a column address, the method comprising the steps of: decoding an incoming address, specifying a cell of interest in each DRAM device in a bank, to designate the bank of DRAM devices each containing the cell of interest; multiplexing the incoming address to generate a complete row address that specifies the row in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and simultaneously specifies the row containing the cell of interest row when the DRAM device has an unequal number of rows and columns; multiplexing the incoming address to generate a complete column address that specifies the column in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and that simultaneously specifies the row containing the cell of interest row when the DRAM device has an unequal number of rows and columns; sequentially applying the complete row address and the complete column address to each DRAM device in the designated bank; decoding only as much of the complete row address at each DRAM device as is necessary, in accordance with the number and columns in the DRAM device, to select the row containing the cell of interest; and decoding only as much of the complete column address at each DRAM device as is necessary, in accordance with the number and columns in the DRAM device, to select the row containing the cell of interest.
Claim 3
Dependent Claim
71 words
The method according to claim 1 wherein the step of multiplexing the incoming address to generate the complete row address includes the steps of: multiplexing the incoming address to establish a row address specifying the row containing the cell of interest in each said DRAM for the condition when said DRAM is asymmetric; and permuting the row address by interchanging highest and lowest order bits to yield the complete row address.
Claim 4
Dependent Claim
50 words
The method according to claim 1 wherein the step of multiplexing the incoming address to generate a complete column address includes the step of multiplexing the incoming address to yield a column address which specifies the column containing the cell of interest for the condition when the DRAM is symmetric.
Claim 5
Dependent Claim
32 words
The method according to claim 1 further including the steps of: establishing the presence of the DRAM devices in each bank; and establishing the density of the DRAM devices in each bank.
Claim 6
Dependent Claim
107 words
The method according to claim 4 wherein the step of determining the presence of the DRAM devices in each bank includes the steps of: writing at least one data pattern into at least one cell known to exist in each possible DRAM device that may be present, the cell having an address which is the same regardless of whether the DRAM device is symmetric or asymmetric: reading said one cell; comparing the contents of said one cell to the data pattern written therein and generating a result indicative of such comparison, and indicating the presence of the DRAM device in accordance with the result of the comparison.
Claim 7
Dependent Claim
120 words
The method according to claim 4 wherein the step of determining the presence of the DRAM devices in each bank includes the steps of: writing each of four separate data patterns into each of four cells, respectively, each cell known to exist in each possible DRAM device that may be present and each cell having an address which is the same irrespective of the DRAM device symmetry; reading each cell; comparing the contents of each cell to a separate one of the four data patterns and generating a result for each cell indicative of whether said separate data pattern is present in the cell; and indicating the presence of the DRAM device in accordance with the result of the comparison.
Claim 8
Dependent Claim
92 words
The method according to claim 4 wherein the step of determining the DRAM device density includes the steps of: writing a data pattern into each of four cells whose addresses are separated by an amount corresponding to the possible variation in the density of the DRAM devices in the banks; reading each of the four cells; comparing the contents of each cell to the data pattern written therein and generating a result indicative of such comparison; and indicating the density of the DRAM device in accordance with the result of each comparison.
Claim 9
Dependent Claim
19 words
The method according to claim 7 wherein each of the four cells is written with a different data pattern.
Claim 10
Independent Claim
324 words
A method for controlling banks of DRAM devices, each DRAM device containing a plurality of memory cells arrayed in rows and columns, each row and column having an individual row and column address, respectively, comprising the steps of: determining which DRAM devices are present; determining how dense each DRAM device is; decoding an incoming address, specifying a cell of interest in each DRAM device in a bank, to designate the bank of DRAM devices each containing the cell of interest; multiplexing the incoming address to generate a complete row address in accordance with the DRAM device density to specify the row in each DRAM device in the designated bank containing the cell of interest for the condition when each said DRAM device has an equal number of rows and columns and that simultaneously specifies the row containing the cell of interest for the condition when the DRAM device has an unequal number of rows and columns; multiplexing the incoming address to generate a complete column address in accordance with the DRAM device density to specify the column in each DRAM device in the designated bank containing the cell of interest for the condition when each said DRAM device has an equal number of rows and columns, and to simultaneously specify the column containing the cell of interest for the condition when the DRAM device has an unequal number of rows and columns; sequentially applying the complete row address and the complete column address to each DRAM device in the designated bank; decoding only as much of the complete row address at each DRAM device as is necessary, in accordance with the number of rows in the DRAM device, to select the row containing the cell of interest; and decoding only as much of the complete column address at each DRAM device as is necessary, in accordance with the number of columns in the DRAM device, to select the column containing the cell of interest.
Claim 11
Independent Claim
324 words
A method for controlling banks of DRAM devices, each DRAM device containing a plurality of memory cells arrayed in rows and columns, each row and column having an individual row and column address, respectively, comprising the steps of: determining which DRAM devices are present; determining how dense each DRAM device is; decoding an incoming address, specifying a cell of interest in each DRAM device in a bank, to designate the bank of DRAM devices each containing the cell of interest; multiplexing the incoming address to generate a complete row address in accordance with the DRAM device density to specify the row in each DRAM device in the designated bank containing the cell of interest for the condition when each said DRAM device has an equal number of rows and columns and that simultaneously specifies the row containing the cell of interest for the condition when the DRAM device has an unequal number of rows and columns; multiplexing the incoming address to generate a complete column address in accordance with the DRAM device density to specify the column in each DRAM device in the designated bank containing the cell of interest for the condition when each said DRAM device has an equal number of rows and columns, and to simultaneously specify the column containing the cell of interest for the condition when the DRAM device has an unequal number of rows and columns; sequentially applying the complete row address and the complete column address to each DRAM device in the designated bank; decoding only as much of the complete row address at each DRAM device as is necessary, in accordance with the number of rows in the DRAM device, to select the row containing the cell of interest; and decoding only as much of the complete column address at each DRAM device as is necessary, in accordance with the number of columns in the DRAM device, to select the column containing the cell of interest.
Claim 12
Dependent Claim
107 words
The method according to claim 9 wherein the step of determining the presence of the DRAM devices in each bank includes the steps of: writing at least one data pattern into at least one cell known to exist in each possible DRAM device that may be present, the cell having an address which is the same regardless of whether the DRAM device is symmetric or asymmetric; reading said one cell; comparing the contents of said one cell to the data pattern written therein and generating a result indicative of such comparison, and indicating the presence of the DRAM device in accordance with the result of the comparison.
Claim 13
Dependent Claim
120 words
The method according to claim 9 wherein the step of determining the presence of the DRAM devices in each bank includes the steps of: writing each of four separate data patterns into each of four cells, respectively, each cell known to exist in each possible DRAM device that may be present and each cell having an address which is the same irrespective of the DRAM device symmetry; reading each cell; comparing the contents of each cell to a separate one of the four data patterns and generating a result for each cell indicative of whether said separate data pattern is present in the cell; and indicating the presence of the DRAM device in accordance with the result of the comparison.
Claim 14
Dependent Claim
91 words
The method according to claim 9 wherein the step of determining the DRAM device density includes the steps of: writing a data pattern into each of four cells whose addresses are separated by an amount corresponding to the possible variation in the density of the DRAM devices in the banks; reading each of the four cells; comparing the contents of each cell to the data pattern written therein and generating a result indicative of such comparison; indicating the density of the DRAM device in accordance with the result of each comparison.
Claim 15
Dependent Claim
19 words
The method according to claim 12 wherein each of the four cells is written with a different data pattern.
Claim 16
Independent Claim
228 words
An apparatus for controlling a plurality of banks of DRAM devices, each DRAM device comprised of a plurality of memory cells arrayed in rows and columns, each cell being uniquely identified by a row address and a column address, the method comprising the steps of: means for decoding an incoming address, specifying a cell of interest in each DRAM device in a bank, to designate the bank of DRAM devices each containing the cell of interest; means for multiplexing the incoming address to generate a complete row address that specifies the row in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and that simultaneously specifies the row containing the cell of interest when the DRAM device has an unequal number of rows and columns, said means also multiplexing the incoming address to generate a complete column address that specifies the column in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and that simultaneously specifies the column containing the cell of interest when DRAM device has an unequal number of rows and columns; and means for sequentially applying the complete row address and the complete column address to each DRAM device in the designated bank.
Claim 17
Independent Claim
228 words
An apparatus for controlling a plurality of banks of DRAM devices, each DRAM device comprised of a plurality of memory cells arrayed in rows and columns, each cell being uniquely identified by a row address and a column address, the method comprising the steps of: means for decoding an incoming address, specifying a cell of interest in each DRAM device in a bank, to designate the bank of DRAM devices each containing the cell of interest; means for multiplexing the incoming address to generate a complete row address that specifies the row in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and that simultaneously specifies the row containing the cell of interest when the DRAM device has an unequal number of rows and columns, said means also multiplexing the incoming address to generate a complete column address that specifies the column in each DRAM device in the designated bank containing the cell of interest when each said DRAM device has an equal number of rows and columns, and that simultaneously specifies the column containing the cell of interest when DRAM device has an unequal number of rows and columns; and means for sequentially applying the complete row address and the complete column address to each DRAM device in the designated bank.
Claim 18
Dependent Claim
22 words
The apparatus according to claim 14 further including means for determining the presence and density of the DRAM devices in the banks.
Claim 19
Dependent Claim
91 words
The apparatus according to claim 15 wherein said means comprises: address-generating means for generating at least one presence address that is valid for every possible DRAM device regardless of its density and for generating a plurality of size addresses, each separate from the other by an amount corresponding to DRAM device density differences; and data generator and comparison means generating at least one data pattern for writing to the presence and size addresses and comparing data read from said presence and size addresses to determine the DRAM device presence and density.
Claim 20
Dependent Claim
63 words
The apparatus according to claim 16 wherein said address-generating means comprises: a first multiplexor for selectively passing at least one presence address; a first buffer for temporarily storing the presence address passed by the first multiplexor; a second multiplexor for selectively passing one of the four size addresses; and a second buffer for temporarily storing the size address passed by the second multiplexor.
Claim 21
Dependent Claim
79 words
The apparatus according to claim 16 wherein the data generator and comparator means comprises: means for supplying at least one data pattern; comparator means for comparing the data pattern supplied by said supplying means to a data pattern read from one of the size and presence addresses and for generating a result in accordance with said comparison; register means for storing the results of said comparator means; and logic means for processing the results held by said register means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |