§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0327309A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Memory apparatus having error correction function

Assignee: NEC Corp
•
Filing: 1989-01-31
•
Granted: —
•
Expires: 2009-01-31
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A memory apparatus having an error correction function, comprises an error correction code generator/checker having a first input for receiving the information to be stored from a data input circuit and a second input. The error correction code generator/checker operates to generator an error correction code on the basis of the information to be stored in the case of writing and to generate an error code on the basis of signals inputted to the second input in the case of reading. A memory section is coupled to the data input circuit and an output of the error correction code generator/checker so as to store the information to be stored and a corresponding error correction code at a designated location of the memory section. A reading circuit is connected to the memory section to read information and an associated error correction code from the memory section for outputting the read-out information and associated error correction to second input of the error correction code generator/checker. A decoder is coupled to the error correction code generator/checker to receive the error code from the error correction code generator/checker and to generate a decoded signal. An error correction circuit is connected to receive an information portion of the read-out signal from the reading circuit so as to correct the received information on the basis of the decoded signal from the decoder. A control circuit is provided for maintaining the data input circuit in an active condition and the reading circuit and the decoder in an inactive condition in the case of writing and on the other hand for maintain the data input circuit in an inactive condition and the reading circuit and decoder in an active condition in the case of reading.

Inventors

  • 👤 Shushi Kanauchi

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 12:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 297 words
A memory apparatus having an error correction function, comprising a data input circuit for receiving information to be stored, an error correction code generator/checker having a first input for receiving the information to be stored from the data input circuit and a second input, the error correction code generator/checker operating to generate an error correction code on the basis of the information to be stored in the case of writing and to generate an error code on the basis of signals inputted to the second input in the case of reading, a memory section coupled to the data input circuit and an output of the error correction code generator/checker so as to store the information to be stored and a corresponding error correction code at a designated location of the memory section, a reading circuit connected to the memory section to read information and an associated error correction code from a designated location of the memory section for outputting the read-out information and associated error correction to the second input of the error correction code generator/checker, a decoder coupled to the error correction code generator/checker to receive the error code from the error correction code generator/checker and to generate a decoded signal, an error correction circuit connected to receive an information portion of the read-out signal from the reading circuit so as to correct the received information on the basis of the decoded signal from the decoder, and a control circuit for maintaining the data input circuit in an active condition and the reading circuit and the decoder in an inactive condition in the case of writing and on the other hand for maintain the data input circuit in an inactive condition and the reading circuit and decoder in an active condition in the case of reading.
Claim 2
Dependent Claim 297 words
A memory apparatus having an error correction function, comprising a data input circuit for receiving information to be stored, an error correction code generator/checker having a first input for receiving the information to be stored from the data input circuit and a second input, the error correction code generator/checker operating to generate an error correction code on the basis of the information to be stored in the case of writing and to generate an error code on the basis of signals inputted to the second input in the case of reading, a memory section coupled to the data input circuit and an output of the error correction code generator/checker so as to store the information to be stored and a corresponding error correction code at a designated location of the memory section, a reading circuit connected to the memory section to read information and an associated error correction code from a designated location of the memory section for outputting the read-out information and associated error correction to the second input of the error correction code generator/checker, a decoder coupled to the error correction code generator/checker to receive the error code from the error correction code generator/checker and to generate a decoded signal, an error correction circuit connected to receive an information portion of the read-out signal from the reading circuit so as to correct the received information on the basis of the decoded signal from the decoder, and a control circuit for maintaining the data input circuit in an active condition and the reading circuit and the decoder in an inactive condition in the case of writing and on the other hand for maintain the data input circuit in an inactive condition and the reading circuit and decoder in an active condition in the case of reading.
Claim 3
Dependent Claim 88 words
An apparatus claimed in Claim 1 wherein the error correction code generator/checker includes a plurality of input lines and at least a pull-­down transistor connected to a line of the input lines which is connected to the output of the reading circuit but not connected to the output of the data input circuit, the pull-down transistor being controlled by the control circuit so as to be maintained in an ON condition in the case of the writing and in an OFF condition in the case of the reading.
Claim 4
Dependent Claim 78 words
An apparatus claimed in Claim 1 wherein in the case of writing, an output of the data circuit is brought into an active condition and respective outputs of the reading circuit and the decoder are brought into a high impedance condition, and in the case of reading, the output of the data input circuit is brought into a high impedance condition and the respective outputs of the reading circuit and the decoder are brought into an active condition.
Claim 5
Dependent Claim 75 words
An apparatus claimed in Claim 1 wherein the error correction code generator/checker includes a plurality of information input lines and a plurality of error correction code input lines, each of the error correction code input lines being connected to a pull-down transistor which is controlled by the control circuit so as to be maintained in an ON condition in the case of the writing and in an OFF condition in the case of the reading.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag