Patent US5385857A successfully refreshed from Google Patents.
US5385857A
Expired / Lapsed
US
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Method of manufacturing a semiconductor device with high packing density and having field effect transistors
Assignee: NXP BV
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Filing: 1992-12-21
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Granted: 1995-01-31
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Expires: 2012-12-21
Abstract
Abstract A method of manufacturing a semiconductor device having a field effect transistor and a device manufactured by this method in which a high packing density can be realized. The field effect transistor includes a gate electrode (31,41) which is separated from a channel region by a first insulating layer (8) and is entirely surrounded by insulating material. For this purpose, a conductive layer (9) which is to form a gate electrode (31,41) is covered with a second insulating layer (10) and both layers are subsequently given the same pattern at least at the area of the channel region. As a result, the gate electrode (31,41) is covered at the upper side with a portion of the second insulating layer (10). The gate electrode (31,41) is laterally insulated by the provision of a third insulating layer (13) which is subsequently etched back anisotropically, whereby a portion (14) thereof remains intact afterwards alongside the side wall of the gate electrode (31,41). At least the source (32,42) or the drain (33,43) of the transistor is provided with an electrical connection (20) which makes contact through a contact window (19) in a further insulating layer (19). Due to the complete insulation of the gate electrode (31,41), the contact window (19) is allowed to overlap the associated gate electrode (31,41), so no alignment tolerances need be taken into account relative to the gate electrode (31,41) for forming this window (19).
Inventors
- 👤 Jose Solo de Zaldivar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
199 words
A method of manufacturing a semiconductor device whereby a field effect transistor is provided at a surface of a semiconductor body, which comprises the steps of: providing a first insulating layer on the surface of the semiconductor body; depositing a conductive layer on the first insulating layer; providing a second insulating layer on the conductive layer; selectively removing the second insulating layer from part of the conductive layer to expose a contact region of the conductive layer; providing an etching mask which at least partly covers said contact region; etching between portions of the etching mask and through the second insulating layer and the conductive layer to form a gate electrode; implanting impurities on both sides of the gate electrode to form a source and a drain region of a first conductivity type mutually separated by a channel region of a second, opposite conductivity type under the gate electrode; providing a third insulating layer over the resultant structure; anisotropically etching the third insulating layer to form at least sidewalls on the gate electrode; forming a contact window over the source and drain regions and a portion of the gate electrode; and providing an electrical connection in the contact window.
Claim 2
Independent Claim
199 words
A method of manufacturing a semiconductor device whereby a field effect transistor is provided at a surface of a semiconductor body, which comprises the steps of: providing a first insulating layer on the surface of the semiconductor body; depositing a conductive layer on the first insulating layer; providing a second insulating layer on the conductive layer; selectively removing the second insulating layer from part of the conductive layer to expose a contact region of the conductive layer; providing an etching mask which at least partly covers said contact region; etching between portions of the etching mask and through the second insulating layer and the conductive layer to form a gate electrode; implanting impurities on both sides of the gate electrode to form a source and a drain region of a first conductivity type mutually separated by a channel region of a second, opposite conductivity type under the gate electrode; providing a third insulating layer over the resultant structure; anisotropically etching the third insulating layer to form at least sidewalls on the gate electrode; forming a contact window over the source and drain regions and a portion of the gate electrode; and providing an electrical connection in the contact window.
Claim 3
Dependent Claim
41 words
A method as claimed in claim 1, characterized in that the third insulating layer is also provided with a contact window at the area of the contact region of the conductive layer and in that an electrical connection is provided therein.
Claim 4
Dependent Claim
56 words
A method as claimed in claim 2, characterized in that at least the contact region of the conductive layer is covered with a dielectric, in that the dielectric is exposed in the contact window, and in that an electrical connection is provided via the contact window on the dielectric so as to form a capacitance electrode.
Claim 5
Dependent Claim
102 words
A method as claimed in claim 1, characterized in that, before the third insulating layer is provided, the semiconductor body on either side of the gate electrode is doped with an impurity of the first conductivity type so as to form a first, comparatively weakly doped portion of the source and the drain, and in that, after the portion along the gate electrode has been formed from the third insulating layer, the semiconductor body is once more doped with an impurity of the first conductivity type so as to form a second, comparatively heavily doped portion to the source and the drain.
Claim 6
Independent Claim
22 words
A method as claimed in claims 1, characterized in that the second insulating layer comprises silicon oxide and is provided by deposition.
Claim 7
Dependent Claim
40 words
A method as claimed in claim 1, characterized in that, after the third insulating layer has been etched back anisotropically, the entire assembly is covered with an etch stop layer relative to which the further insulating layer is selectively etchable.
Claim 8
Dependent Claim
27 words
A method as claimed in claim 6, characterized in that the etch stop layer comprises a material from the group consisting of silicon nitride and aluminum oxide.
Claim 9
Dependent Claim
64 words
A method as claimed in claim 6, characterized in that a layer of flow glass is used for the third insulating layer, in that subsequently said contact window is provided therein and a heat treatment is carried out whereby the further insulating layer flows out, and in that the etch stop layer is not removed from the contact window until after the heat treatment.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |