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US5384271A
Expired / Lapsed
US
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Method for reduction of off-current in thin film transistors
Assignee: General Electric Co
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Filing: 1993-10-04
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Granted: 1995-01-24
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Expires: 2013-10-04
Abstract
Abstract A method of fabricating a thin film transistor having reduced off-current leakage includes the steps of forming a TFT body with a channel region disposed between a source electrode and a drain electrode and then passivating the exposed portion of the channel region. The passivation includes the steps of wet etching the exposed portions of the channel region in an hydrofluoric acid etchant for a first selected etch time; dry etching the exposed channel region in a reactive ion etching procedure for a second selected etch time; wet etching the channel region again with hydrofluoric acid for a third selected etch time; and then treating the channel region with a cleansing agent, such as photoresist stripper; and annealing the exposed portion of the channel region.
Inventors
- 👤 Robert F. Kwasnick
- 👤 George E. Possin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
167 words
A method of fabricating a thin film transistor (TFT) having relatively low off-current comprising the steps of: forming a TFT body having a gate electrode, a gate dielectric layer disposed over said gate electrode, a semiconductor layer disposed over said gate dielectric layer, a doped semiconductor layer disposed over said semiconductor layer, and a source-drain metal layer disposed over said doped semiconductor layer; forming a channel region in said TFT body, said channel region being exposed and defined by etching said source-drain metal layer, the underlying doped semiconductor layer, and a portion of the underlying semiconductor layer so as to form source and drain electrodes; and passivating the channel region, the step of passivating further comprising the steps of wet etching the exposed channel region for a first etch time, dry etching the exposed channel region for a second etch time, wet etching the exposed channel region for a third etch time, treating the exposed channel region with a cleansing solution, and annealing the exposed channel region.
Claim 2
Independent Claim
167 words
A method of fabricating a thin film transistor (TFT) having relatively low off-current comprising the steps of: forming a TFT body having a gate electrode, a gate dielectric layer disposed over said gate electrode, a semiconductor layer disposed over said gate dielectric layer, a doped semiconductor layer disposed over said semiconductor layer, and a source-drain metal layer disposed over said doped semiconductor layer; forming a channel region in said TFT body, said channel region being exposed and defined by etching said source-drain metal layer, the underlying doped semiconductor layer, and a portion of the underlying semiconductor layer so as to form source and drain electrodes; and passivating the channel region, the step of passivating further comprising the steps of wet etching the exposed channel region for a first etch time, dry etching the exposed channel region for a second etch time, wet etching the exposed channel region for a third etch time, treating the exposed channel region with a cleansing solution, and annealing the exposed channel region.
Claim 3
Dependent Claim
35 words
The method of claim 1 wherein the steps of wet etching said exposed channel region for a first etch time and for a third etch time further comprises applying an etchant comprising hydrofluoric acid (HF).
Claim 4
Dependent Claim
24 words
The method of claim 2 wherein the step of dry etching said exposed channel region comprises reactive ion etching (RIE) said exposed channel region.
Claim 5
Dependent Claim
12 words
The method of claim 3 wherein said cleansing solution comprises photoresist stripper.
Claim 6
Dependent Claim
12 words
The method of claim 3 wherein said cleansing solution comprises distilled water.
Claim 7
Dependent Claim
33 words
The method of claim 3 wherein the step of annealing said exposed channel region comprises baking said TFT body at a temperature of about 250° C. for a period of about 30 minutes.
Claim 8
Dependent Claim
21 words
The method of claim 3 wherein said first etch time is in the range between about 20 seconds to 90 seconds.
Claim 9
Dependent Claim
21 words
The method of claim 3 wherein said second etch time is in the range between about 15 seconds to 60 seconds.
Claim 10
Dependent Claim
21 words
The method of claim 3 wherein said third etch time is in the range between about 30 seconds to 90 seconds.
Claim 11
Dependent Claim
41 words
The method of claim 4 wherein the step of treating the exposed channel region with photoresist stripper comprises applying said photoresist stripper to said exposed channel region for a period of about 5 minutes and a temperature of about 80° C.
Claim 12
Dependent Claim
14 words
The method of claim 1 wherein said doped semiconductor material comprises heavily doped n+silicon.
Claim 13
Dependent Claim
12 words
The method of claim 1 wherein said semiconductor material comprises amorphous silicon.
Claim 14
Dependent Claim
25 words
The method of claim 3 further comprising the step of depositing a layer of dielectric passivation material over said TFT body and said channel region.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
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