US5281546A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a thin film transistor using hydrogen plasma treatment of the intrinsic silicon/doped layer interface
Assignee: General Electric Co
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Filing: 1992-09-02
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Granted: 1994-01-25
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Expires: 2012-09-02
Abstract
Abstract A method of fabricating a thin film transistor (TFT) including the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer over the gate conductor; depositing a layer of amorphous silicon over the gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+ doped silicon over the treated amorphous silicon surface such that an interface is formed between the amorphous silicon and the n+ doped layer that has relatively low contact resistance; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The TFT material layers are preferably deposited by plasma enhanced chemical vapor deposition. The hydrogen plasma treatment is advantageously used both when vacuum is maintained during the various deposition steps, and when vacuum is broken, for the purposes of patterning the amorphous silicon layer or the like, such that the amorphous silicon layer is passivated with the hydrogen plasma treatment prior to the deposition of the n+ doped layer.
Inventors
- 👤 George E. Possin
- 👤 Robert F. Kwasnick
- 👤 Brian W. Giambattista
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; H10P; H10P95/00; H10P95/94; Y; Y10; Y10S; Y10S438/00; Y10S438/909; Y10S438/91
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
123 words
A method of fabricating a thin film transistor (TFT) comprising the steps of: forming a gate conductor on an upper surface of a substrate; depositing a gate dielectric layer having a selected thickness over the gate conductor; depositing a layer of amorphous silicon over said gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+doped amorphous silicon over the treated amorphous silicon layer such that an interface is established between said amorphous silicon and said n+doped layer having relatively low contact resistance; depositing a layer of source/drain metallization over the n+doped silicon layer; and patterning the source/drain metallization layer and underlying portions of said n+doped layer to form respective source and drain electrodes.
Claim 2
Independent Claim
123 words
A method of fabricating a thin film transistor (TFT) comprising the steps of: forming a gate conductor on an upper surface of a substrate; depositing a gate dielectric layer having a selected thickness over the gate conductor; depositing a layer of amorphous silicon over said gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+doped amorphous silicon over the treated amorphous silicon layer such that an interface is established between said amorphous silicon and said n+doped layer having relatively low contact resistance; depositing a layer of source/drain metallization over the n+doped silicon layer; and patterning the source/drain metallization layer and underlying portions of said n+doped layer to form respective source and drain electrodes.
Claim 3
Dependent Claim
64 words
The method of claim 1 wherein the step of treating the exposed surface of the amorphous silicon with a hydrogen plasma further comprises the steps of: disposing the exposed amorphous silicon surface in a reactor vessel; applying the hydrogen plasma to the exposed surface at a selected flow rate and a selected pressure, for a selected exposure time at a selected plasma power density.
Claim 4
Dependent Claim
88 words
The method of claim 2 wherein: said reactor vessel has an electrode to substrate separation of about 2.8 cm and an electrode cross-sectional area of about 4560 cm 2 ; said selected hydrogen plasma flow rate is between about 30 sccm and 2000 sccm; the selected pressure of said hydrogen plasma is between about 200 mTorr and 2000 mTorr; said selected exposure time is between about 2 minutes and 60 minutes; and said selected plasma power density is between about 10 mW/cm 2 and 440 mW/cm 2 .
Claim 5
Dependent Claim
36 words
The method of claim 3 wherein the steps of depositing a gate dielectric layer and depositing a layer of amorphous silicon each comprise plasma enhanced chemical vapor deposition of said respective layers in said reactor vessel.
Claim 6
Dependent Claim
53 words
The method of claim 4 further comprising the steps of maintaining vacuum in said reactor vessel between each of the steps of depositing a layer of amorphous silicon, treating the exposed surface of the amorphous silicon with hydrogen plasma, and depositing a layer of n+doped amorphous silicon over the treated amorphous silicon layer.
Claim 7
Dependent Claim
68 words
The method of claim 4 further comprising the steps of: processing the materials disposed on the substrate, said processing including breaking vacuum in said reactor vessel after depositing said layer of amorphous silicon; placing the substrate and the processed materials thereon in said reactor vessel; then establishing vacuum in said reactor vessel; and initiating the step of treating the exposed surface of the amorphous silicon with hydrogen plasma.
Claim 8
Dependent Claim
86 words
The method of claim 6 wherein the processing of materials disposed on the substrate comprises the steps of: depositing a second dielectric layer over said layer of amorphous silicon; breaking vacuum in said reactor vessel; depositing a photoresist layer over said second dielectric layer; patterning said photoresist; and selectively etching said second dielectric layer to form a channel plug underlying the pattered photoresist such that the dimensions of said channel plug correspond to the desired overlap of said source and drain electrodes over said gate conductor.
Claim 9
Dependent Claim
32 words
The method of claim 6 further comprising the step of cleaning the amorphous silicon with hydrofluoric acid (HF) prior to placing the substrate and the processed layers thereon into said reactor vessel.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |