US5381046A
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US
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Stacked conductive resistive polysilicon lands in multilevel semiconductor chips
Assignee: International Business Machines Corp
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Filing: 1993-12-01
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Granted: 1995-01-10
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Expires: 2013-12-01
Abstract
Abstract A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al 2 O 3 . The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.
Inventors
- 👤 Carl Cederbaum
- 👤 Roland Chanclou
- 👤 Myriam Combes
- 👤 Patrick Mone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 01:01
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/056; H10W20/0698; H10W20/071; H10W20/081; H10W20/40; H10W20/41; H10W20/42; H10W20/44; H10W20/4451; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
160 words
A semiconductor structure having a semiconductor substrate (18/19) and completed the Master Slice processing steps, said structure having active regions (21) of devices (T1) formed therein and polysilicon lines (23-1) formed thereon, comprising the following successive elements: a first thick passivating layer, said first thick passivating layer including an etch stop layer of intrinsic polysilicon formed on said substrate, a layer of phosphosilicate glass (PSG) formed on said etch stop layer, a diffusion barrier layer on said PSG layer and said first passivating layer having a plurality of first metal contact studs (30-1) therein contacting at least one of said active regions (21) and at least one of said polysilicon lines (23-1); a surface of said first contact studs being coplanar with a surface of said first thick passivating layer; and a plurality of polysilicon lands (31-1) on the coplanar surface, at least one of said polysilicon lands being in contact with at least one of said first contact studs.
Claim 2
Dependent Claim
160 words
A semiconductor structure having a semiconductor substrate (18/19) and completed the Master Slice processing steps, said structure having active regions (21) of devices (T1) formed therein and polysilicon lines (23-1) formed thereon, comprising the following successive elements: a first thick passivating layer, said first thick passivating layer including an etch stop layer of intrinsic polysilicon formed on said substrate, a layer of phosphosilicate glass (PSG) formed on said etch stop layer, a diffusion barrier layer on said PSG layer and said first passivating layer having a plurality of first metal contact studs (30-1) therein contacting at least one of said active regions (21) and at least one of said polysilicon lines (23-1); a surface of said first contact studs being coplanar with a surface of said first thick passivating layer; and a plurality of polysilicon lands (31-1) on the coplanar surface, at least one of said polysilicon lands being in contact with at least one of said first contact studs.
Claim 3
Dependent Claim
17 words
The semiconductor structure of claim 1 wherein at least one of said polysilicon lands is highly resistive.
Claim 4
Dependent Claim
62 words
The semiconductor structure of claim 1 or 2 further including: a second thick passivating layer (34/35) above the structure having a plurality of second metal contact-studs (37-1) therein contacting electrically at least one of said polysilicon lands and one of said first contact studs; a surface of said second contact studs being coplanar with a surface of said second thick passivating layer.
Claim 5
Dependent Claim
38 words
The semiconductor structure of claim 3 further including: a plurality of metal lands (38-1 . . . ) above said second thick passivating layer (34/35) in contact with said second contact studs; and a final insulating film (39).
Claim 6
Dependent Claim
39 words
The semiconductor structure of claim 1 wherein said devices are FETs and a plurality of said polysilicon lines are on an insulator, said insulator being on said substrate, said plurality of polysilicon lines forming gate electrodes of said FETs.
Claim 7
Dependent Claim
17 words
The semiconductor structure of claim 1 wherein at least one of said polysilicon lands is highly conductive.
Claim 8
Dependent Claim
17 words
The semiconductor structure of claim 2 wherein at least one of said polysilicon lands is highly conductive.
Claim 9
Dependent Claim
162 words
A semiconductor structure having a semiconductor substrate (18/19) and completed the Master Slice processing steps, said structure having active regions (21) of devices (T1) formed therein and polysilicon lines (23-1) formed thereon, comprising the following successive elements: a first thick passivating layer, said first thick passivating layer including an etch stop layer of Al 2 O 3 formed on said substrate, a layer of phosphosilicate glass (PSG) formed on said etch stop layer, a diffusion barrier layer on said PSG layer and said first passivating layer having a plurality of first metal contact studs (30-1) therein contacting at least one of said active regions (21) and at least one of said polysilicon lines (23-1); a surface of said first contact studs being coplanar with a surface of said first thick passivating layer; and a plurality of polysilicon lands (31-1) on the coplanar surface, at least one of said polysilicon lands being in contact with at least one of said first contact studs.
Claim 10
Dependent Claim
162 words
A semiconductor structure having a semiconductor substrate (18/19) and completed the Master Slice processing steps, said structure having active regions (21) of devices (T1) formed therein and polysilicon lines (23-1) formed thereon, comprising the following successive elements: a first thick passivating layer, said first thick passivating layer including an etch stop layer of Al 2 O 3 formed on said substrate, a layer of phosphosilicate glass (PSG) formed on said etch stop layer, a diffusion barrier layer on said PSG layer and said first passivating layer having a plurality of first metal contact studs (30-1) therein contacting at least one of said active regions (21) and at least one of said polysilicon lines (23-1); a surface of said first contact studs being coplanar with a surface of said first thick passivating layer; and a plurality of polysilicon lands (31-1) on the coplanar surface, at least one of said polysilicon lands being in contact with at least one of said first contact studs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |