Technique for providing improved signal integrity on computer systems interface buses

Claim 2

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected directions, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal, and means for controlling the slope of the trailing edge of said operation control signal, and said circuitry being arranged to have a substantially small input capacitance.

Claim 3

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal, and means for controlling the slope of the trailing edge of said operation control signal, and said circuitry being arranged to introduce a substantially small propagation delay of an operation control signal being transmitted through said buffer unit.

Claim 4

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal, and means for controlling the slope of the trailing edge of said operation control signal, and said circuitry being arranged to introduce a substantially small propagation delay of an operation control signal being transmitted through said buffer unit.

Claim 5

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and said circuitry including an input resistance network connected to said bus means for responding to an operation control signal to be transmitted through said buffer unit; a non-reciprocal amplifier connected to said input resistance network for amplifying the pulse waveform of said operation control signal; a resistance-capacitance circuit being connected to said non-reciprocal amplifier and having a selected time constant for controlling the slope of the trailing edge of said amplified pulse waveform; and a transistor output circuit connected to said resistance-capacitance circuit for supplying said amplified pulsed waveform signal at the collector thereof, the voltage at said collector being arranged to have a sufficiently high level so as to cause the signal pulse waveform to return to a final signal level which is substantially beyond said selected threshold level.

Claim 6

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and said circuitry including an input resistance network connected to said bus means for responding to an operation control signal to be transmitted through said buffer unit; a non-reciprocal amplifier connected to said input resistance network for amplifying the pulse waveform of said operation control signal; a resistance-capacitance circuit being connected to said non-reciprocal amplifier and having a selected time constant for controlling the slope of the trailing edge of said amplified pulse waveform; and a transistor output circuit connected to said resistance-capacitance circuit for supplying said amplified pulsed waveform signal at the collector thereof, the voltage at said collector being arranged to have a sufficiently high level so as to cause the signal pulse waveform to return to a final signal level which is substantially beyond said selected threshold level.

Claim 7

An interface system in accordance with claim 3 wherein said transistor output circuit acts as an open collector circuit, the collector being connected to an output resistance network.

Claim 8

An interface system in accordance with claim 3 wherein the collector of said transfer output circuit is connected to voltage source via a collector resistance.

Claim 9

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and wherein said system includes a plurality of groups of said peripheral units, each group having said buffer unit connected at the host computer side of its associated group of peripheral units.

Claim 10

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and wherein said system includes a plurality of groups of said peripheral units, each group having said buffer unit connected at the host computer side of its associated group of peripheral units.

Claim 11

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and wherein each said operation control signal pulse waveform is such that the signal level thereof varies between a high signal and a low signal, the trailing edge of said operation control signal being returned from said low signal level to a high final signal level in a pull-up signal operation.

Claim 12

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level, said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and wherein each said operation control signal pulse waveform is such that the signal level thereof varies between a high signal and a low signal, the trailing edge of said operation control signal being returned from said low signal level to a high final signal level in a pull-up signal operation.

Claim 13

An interface system in accordance with claim 7 wherein said high signal level is substantially higher than said selected threshold signal level.

Claim 14

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and wherein said system includes a plurality of bus means connected between said host computer unit and said groups of peripheral units, at least one of said bus means transmitting a first operation control signal from said peripheral units to said host computer unit and at least one of said bus means transmitting a second operation control signal from said host unit to said groups of peripheral units.

Claim 15

An interface system for transmitting operation control signals in a selected direction between a host computer unit and a plurality of peripheral units, said operation control signals having a pulse waveform the trailing edge of which returns to a selected final signal level said interface system comprising: bus means connected to said host computer unit and to said plurality of peripheral units, said peripheral units being arranged for connection to said bus means in selected groups thereof; a buffer unit connected between and in series with said bus means and host computer unit, said buffer unit including circuitry for providing for the transmission of said operation control signals therethrough in a said selected direction, said circuitry including means responsive only to an operation control signal supplied thereto for amplifying said operation control signal to control the final signal level of said operation control signal and means for controlling the slope of the trailing edge of said operation control signal, and wherein said system includes a plurality of bus means connected between said host computer unit and said groups of peripheral units, at least one of said bus means transmitting a first operation control signal from said peripheral units to said host computer unit and at least one of said bus means transmitting a second operation control signal from said host unit to said groups of peripheral units.

Claim 16

An interface system in accordance with claim 9 wherein each said first operation control signal is a request signal and each said second operation control signal is an acknowledge signal.