Method of constructing reduced size highly integrated static random access memory with double vertical channel structure

Claim 1

A static random access memory comprising: a substrate of a first conductivity type having at its surface a first impurity diffusion region of a second conductivity type formed to have a predetermined width and a predetermined thickness; a pair of first layers of the first conductivity type formed at positions spaced away from the center of the first impurity diffusion region in opposite horizontal directions, at a first predetermined distance, respectively, each first layer being provided at its surface with a second impurity diffusion region of the second conductivity type having a predetermined width and a predetermined depth; a pair of second layers of the second conductivity type formed at positions spaced away from the center of the first impurity diffusion region in opposite horizontal directions, at a second predetermined distance, respectively, each second layer being provided at its surface with a third impurity diffusion region of the second conductivity type having a predetermined width and a predetermined depth; a ground electrode extending vertically from a center portion of the first impurity diffusion region to a top surface level of the second layers and having a predetermined width; a pair of first gate electrodes formed at opposite sides of the ground electrode, respectively, to have the same height as that of the ground electrode; a pair of second gate electrodes formed between each first gate electrode and an inner side surface of each corresponding second layer facing the first gate electrode, to have the same height as that of the ground electrode; a pair of first insulating regions, wherein each region is formed between the ground electrode and a second gate electrode and adapted to insulate each corresponding first gate electrode; a pair of second insulating regions, wherein each region is formed between a first gate electrode and an inner side surface of each corresponding second layer facing the first gate electrode and adapted to insulate each corresponding second gate electrode; a pair of load resistors formed at opposite outer side surfaces of the second layers through an insulating layer, respectively, each load resistor being in contact with a second impurity diffusion region; and a pair third insulating regions, wherein each region is formed on an outer side surface of the first layer and on a corresponding load resistor.