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US5376568A
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Method of fabricating high voltage complementary metal oxide semiconductor transistors
Assignee: United Microelectronics Corp
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Filing: 1994-01-25
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Granted: 1994-12-27
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Expires: 2014-01-25
Abstract
Abstract A method for manufacturing CMOS transistors for integrated circuits which have metal gates and heavily doped source and drain electrode regions, thereby improving their resisting capability to a high voltage while reducing cycle time for manufacture. As a result, the performance of the transistors is improved and the cost of manufacture is reduced.
Inventors
- 👤 Sheng-Hsing Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/60; H10D30/601; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D64/00; H10D64/01; H10D64/017; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
A method for fabricating an NMOS transistor on an N type substrate, comprising the steps of: (a) forming a P well in a predetermined region of said substrate; (b) implanting N type impurity into predetermined regions in the P well, to form two N - drifting regions; (c) implanting P type impurity into at least one predetermined regions in the P well, to form at least one P - drifting region; (d) implanting N type impurity into predetermined regions in the N - drifting regions, to form N + source and drain electrodes for said NMOS transistor; (e) implanting P type impurity into the at least one P - drifting region, to form at least one P + contact region of the P well; (f) forming a field oxide layer over the N - drifting regions, the N + source and drain electrodes, the P - drifting region, and the at least one P + contact region; (g) forming a gate oxide layer over the field oxide layer and between the N - drifting regions; and (h) forming a metal gate for said NMOS transistor over the gate oxide layer.
Claim 2
Independent Claim
190 words
A method for fabricating an NMOS transistor on an N type substrate, comprising the steps of: (a) forming a P well in a predetermined region of said substrate; (b) implanting N type impurity into predetermined regions in the P well, to form two N - drifting regions; (c) implanting P type impurity into at least one predetermined regions in the P well, to form at least one P - drifting region; (d) implanting N type impurity into predetermined regions in the N - drifting regions, to form N + source and drain electrodes for said NMOS transistor; (e) implanting P type impurity into the at least one P - drifting region, to form at least one P + contact region of the P well; (f) forming a field oxide layer over the N - drifting regions, the N + source and drain electrodes, the P - drifting region, and the at least one P + contact region; (g) forming a gate oxide layer over the field oxide layer and between the N - drifting regions; and (h) forming a metal gate for said NMOS transistor over the gate oxide layer.
Claim 3
Independent Claim
180 words
A method for fabricating a high voltage PMOS transistor on an N type substrate, comprising the steps of: (a) implanting P type impurity into predetermined regions in said substrate, to form two P - drifting regions; (b) implanting N type impurity into at least one predetermined regions in said substrate, to form at least one N - drifting region; (c) implanting N type impurity into the at least one N - drifting region, to form at least one N + contact region of said substrate; (d) implanting P type impurity into predetermined regions in the P - drifting regions, to form P + source and drain electrodes for said PMOS transistor; (e) forming a field oxide layer over the at least one N - drifting region, the at least one N + contact region, the P - drifting regions, and the P + source and drain electrodes; (f) forming a gate oxide layer over the field oxide layer and between the P - drifting regions; and (g) forming a metal gate for said PMOS transistor over the gate oxide layer.
Claim 4
Independent Claim
180 words
A method for fabricating a high voltage PMOS transistor on an N type substrate, comprising the steps of: (a) implanting P type impurity into predetermined regions in said substrate, to form two P - drifting regions; (b) implanting N type impurity into at least one predetermined regions in said substrate, to form at least one N - drifting region; (c) implanting N type impurity into the at least one N - drifting region, to form at least one N + contact region of said substrate; (d) implanting P type impurity into predetermined regions in the P - drifting regions, to form P + source and drain electrodes for said PMOS transistor; (e) forming a field oxide layer over the at least one N - drifting region, the at least one N + contact region, the P - drifting regions, and the P + source and drain electrodes; (f) forming a gate oxide layer over the field oxide layer and between the P - drifting regions; and (g) forming a metal gate for said PMOS transistor over the gate oxide layer.
Claim 5
Independent Claim
190 words
A method for fabricating an PMOS transistor on an P type substrate, comprising the steps of: (a) forming a N well in a predetermined region of said substrate; (b) implanting P type impurity into predetermined regions in the N well, to form two P - drifting regions; (c) implanting N type impurity into at least one predetermined regions in the N well, to form at least one N - drifting region; (d) implanting P type impurity into predetermined regions in the P - drifting regions, to form P + source and drain electrodes for said PMOS transistor; (e) implanting N type impurity into the at least one N - drifting region, to form at least one N + contact region of the N well; (f) forming a field oxide layer over the P - drifting regions, the P + source and drain electrodes, the N - drifting region, and the at least one N + contact region; (g) forming a gate oxide layer over the field oxide layer and between the P - drifting regions; and (h) forming a metal gate for said PMOS transistor over the gate oxide layer.
Claim 6
Independent Claim
190 words
A method for fabricating an PMOS transistor on an P type substrate, comprising the steps of: (a) forming a N well in a predetermined region of said substrate; (b) implanting P type impurity into predetermined regions in the N well, to form two P - drifting regions; (c) implanting N type impurity into at least one predetermined regions in the N well, to form at least one N - drifting region; (d) implanting P type impurity into predetermined regions in the P - drifting regions, to form P + source and drain electrodes for said PMOS transistor; (e) implanting N type impurity into the at least one N - drifting region, to form at least one N + contact region of the N well; (f) forming a field oxide layer over the P - drifting regions, the P + source and drain electrodes, the N - drifting region, and the at least one N + contact region; (g) forming a gate oxide layer over the field oxide layer and between the P - drifting regions; and (h) forming a metal gate for said PMOS transistor over the gate oxide layer.
Claim 7
Independent Claim
180 words
A method for fabricating a high voltage NMOS transistor on an P type substrate, comprising the steps of: (a) implanting N type impurity into predetermined regions in said substrate, to form two N - drifting regions; (b) implanting P type impurity into at least one predetermined regions in said substrate, to form at least one P - drifting region; (c) implanting P type impurity into the at least one P - drifting region, to form at least one P + contact region of said substrate; (d) implanting N type impurity into predetermined regions in the N - drifting regions, to form N + source and drain electrodes for said NMOS transistor; (e) forming a field oxide layer over the at least one P - drifting region, the at least one P + contact region, the N - drifting regions, and the N + source and drain electrodes; (f) forming a gate oxide layer over the field oxide layer and between the N - drifting regions; and (g) forming a metal gate for said NMOS transistor over the gate oxide layer.
Claim 8
Independent Claim
180 words
A method for fabricating a high voltage NMOS transistor on an P type substrate, comprising the steps of: (a) implanting N type impurity into predetermined regions in said substrate, to form two N - drifting regions; (b) implanting P type impurity into at least one predetermined regions in said substrate, to form at least one P - drifting region; (c) implanting P type impurity into the at least one P - drifting region, to form at least one P + contact region of said substrate; (d) implanting N type impurity into predetermined regions in the N - drifting regions, to form N + source and drain electrodes for said NMOS transistor; (e) forming a field oxide layer over the at least one P - drifting region, the at least one P + contact region, the N - drifting regions, and the N + source and drain electrodes; (f) forming a gate oxide layer over the field oxide layer and between the N - drifting regions; and (g) forming a metal gate for said NMOS transistor over the gate oxide layer.
References Cited (Backward Citations)
US4285116A
Cited
US4780428A
Cited
US4978628A
Cited
US4795716A
Cited
US5047358A
Cited
US5169796A
Cited
US5242841A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-12-26 | 1998-06-27 | 1998-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-26 | 2002-06-27 | 2002-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-26 | 2006-06-27 | 2006-12-27 | $7700.00 | Window Closed / Lapsed |