Test circuit of input architecture of erasable and programmable logic device

Claim 1

In an Erasable and Programmable Logic Device comprising a plurality of input architectures for transmitting input data with a certain configuration type of the input architecture, a plurality of input lines provided from the input architectures, a Programmable Logic Array connected to the input lines, and an Input/Output Macrocell connected between the Programmable Logic Array and an input/output pin, the improvement comprising a test circuit of the input architectures comprising: an extra test line; a plurality of EPROM (Erasable Programmable Read Only Memory) transistors each having respectively a drain thereof connected to the extra test line and a gate thereof connected to an input line provided from one of said input architectures; sensing means connected to the extra test line, for sensing a state of the extra test line and producing a transmitted signal representing the state of the extra test line; and a buffer circuit connected to the sensing means, for outputting the transmitted signal from the sensing means to the Input/Output pin.