Solid state memory device capable of providing data signals on 2N data lines or N data lines

Claim 2

In a solid state memory device responsive to a control signal for providing 2N data signals simultaneously on 2N external data signal lines, or providing N data signals simultaneously on N contiguous of the 2N external data signal lines, wherein said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit means divided into two groups; each memory integrated circuit means having an addressable memory circuit for providing N data signals simultaneously on N internal data signal lines in response to an address signal; and multiplexer means for receiving said N internal data signal lines, and the control signal, and in response thereto for providing N data signals simultaneously on N external data signal lines, or N/2 data signals simultaneously on one of two groups of N/2 contiguous external data signal lines; and means for grouping one of the two groups of N/2 contiguous external data signal lines of one group of memory integrated circuit means with one of the two groups of N/2 contiguous external data signal lines of the second group of memory integrated circuit means to form a first N contiguous external data signal lines of the device, and grouping another of the two groups of N/2 contiguous external data signal lines of one group of memory integrated circuit means with another of the two groups of N/2 contiguous external data signal lines of the second group of memory integrated circuit means to form a second N external contiguous data signal lines of the device.

Claim 3

The device of claim 1 wherein said multiplexer means of each memory integrated circuit means also receives an address control signal and in response thereto for providing N/2 data signals on one of the two N/2 external data signal lines.

Claim 4

A solid state peripheral storage device for receiving a plurality of address signals supplied on an address bus, an address control signal and a control signal, said device for providing 2N data signals simultaneously on 2N data signal lines, or N data signals simultaneously on one group of N contiguous data signal lines; said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit chips, divided into two groups; each chip comprising: an addressable memory circuit for providing N data signals simultaneously on two N/2 internal data signal lines in response to the address signals supplied on the address bus; multiplexer means for receiving the N data signals on the two N/2 internal data signal lines, the control signal and the address control signal and for providing: N data signals simultaneously on two N/2 external data signal lines in response to the control signal being in one state; or a first collection of N/2 data signals from one of the two N/2 internal data signal lines to one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in one state; a second collection of N/2 data signals from another of the two N/2 internal data signal lines to said one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in another state; means for grouping said one of the two N/2 external data signal lines of one group of memory chips with said one of the two N/2 external data signal lines of another group of memory chips to form the one group of N contiguous data signal lines.

Claim 5

A solid state peripheral storage device for receiving a plurality of address signals supplied on an address bus, an address control signal and a control signal, said device for providing 2N data signals simultaneously on 2N data signal lines, or N data signals simultaneously on one group of N contiguous data signal lines; said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit chips, divided into two groups; each chip comprising: an addressable memory circuit for providing N data signals simultaneously on two N/2 internal data signal lines in response to the address signals supplied on the address bus; multiplexer means for receiving the N data signals on the two N/2 internal data signal lines, the control signal and the address control signal and for providing: N data signals simultaneously on two N/2 external data signal lines in response to the control signal being in one state; or a first collection of N/2 data signals from one of the two N/2 internal data signal lines to one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in one state; a second collection of N/2 data signals from another of the two N/2 internal data signal lines to said one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in another state; means for grouping said one of the two N/2 external data signal lines of one group of memory chips with said one of the two N/2 external data signal lines of another group of memory chips to form the one group of N contiguous data signal lines.

Claim 6

The device of claim 3 wherein each memory circuit of each chip comprises an array of electrically alterable programmable cell.