US5373467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state memory device capable of providing data signals on 2N data lines or N data lines
Assignee: Silicon Storage Technology Inc
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Filing: 1993-11-10
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Granted: 1994-12-13
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Expires: 2013-11-10
Abstract
Abstract A solid state peripheral storage device in compliance with the PCMCIA standard provides data signals on either 16 data signal lines or 8 data signal lines. The device has a plurality of even number of substantially identical memory integrated circuit chips divided into two groups. Each of the memory integrated circuit chips provides 8 data signal lines divided into two groups of 4 data signal lines. One of the group of 4 data signal lines from one of the group of memory chips is grouped with one of the 4 data signal lines from the other group of memory chips to form a first group of 8 contiguous bus of data signal lines. The other group of 4 data signal lines from one group of memory chips is also collected with 4 data signal lines from the other group of memory chips to form a second group of 8 contiguous data signal lines. The two groups of 8 contiguous data signal lines are grouped together to form the bus of 16 data signal lines.
Inventors
- 👤 Ping Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
252 words
In a solid state memory device responsive to a control signal for providing 2N data signals simultaneously on 2N external data signal lines, or providing N data signals simultaneously on N contiguous of the 2N external data signal lines, wherein said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit means divided into two groups; each memory integrated circuit means having an addressable memory circuit for providing N data signals simultaneously on N internal data signal lines in response to an address signal; and multiplexer means for receiving said N internal data signal lines, and the control signal, and in response thereto for providing N data signals simultaneously on N external data signal lines, or N/2 data signals simultaneously on one of two groups of N/2 contiguous external data signal lines; and means for grouping one of the two groups of N/2 contiguous external data signal lines of one group of memory integrated circuit means with one of the two groups of N/2 contiguous external data signal lines of the second group of memory integrated circuit means to form a first N contiguous external data signal lines of the device, and grouping another of the two groups of N/2 contiguous external data signal lines of one group of memory integrated circuit means with another of the two groups of N/2 contiguous external data signal lines of the second group of memory integrated circuit means to form a second N external contiguous data signal lines of the device.
Claim 2
Dependent Claim
252 words
In a solid state memory device responsive to a control signal for providing 2N data signals simultaneously on 2N external data signal lines, or providing N data signals simultaneously on N contiguous of the 2N external data signal lines, wherein said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit means divided into two groups; each memory integrated circuit means having an addressable memory circuit for providing N data signals simultaneously on N internal data signal lines in response to an address signal; and multiplexer means for receiving said N internal data signal lines, and the control signal, and in response thereto for providing N data signals simultaneously on N external data signal lines, or N/2 data signals simultaneously on one of two groups of N/2 contiguous external data signal lines; and means for grouping one of the two groups of N/2 contiguous external data signal lines of one group of memory integrated circuit means with one of the two groups of N/2 contiguous external data signal lines of the second group of memory integrated circuit means to form a first N contiguous external data signal lines of the device, and grouping another of the two groups of N/2 contiguous external data signal lines of one group of memory integrated circuit means with another of the two groups of N/2 contiguous external data signal lines of the second group of memory integrated circuit means to form a second N external contiguous data signal lines of the device.
Claim 3
Dependent Claim
40 words
The device of claim 1 wherein said multiplexer means of each memory integrated circuit means also receives an address control signal and in response thereto for providing N/2 data signals on one of the two N/2 external data signal lines.
Claim 4
Dependent Claim
293 words
A solid state peripheral storage device for receiving a plurality of address signals supplied on an address bus, an address control signal and a control signal, said device for providing 2N data signals simultaneously on 2N data signal lines, or N data signals simultaneously on one group of N contiguous data signal lines; said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit chips, divided into two groups; each chip comprising: an addressable memory circuit for providing N data signals simultaneously on two N/2 internal data signal lines in response to the address signals supplied on the address bus; multiplexer means for receiving the N data signals on the two N/2 internal data signal lines, the control signal and the address control signal and for providing: N data signals simultaneously on two N/2 external data signal lines in response to the control signal being in one state; or a first collection of N/2 data signals from one of the two N/2 internal data signal lines to one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in one state; a second collection of N/2 data signals from another of the two N/2 internal data signal lines to said one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in another state; means for grouping said one of the two N/2 external data signal lines of one group of memory chips with said one of the two N/2 external data signal lines of another group of memory chips to form the one group of N contiguous data signal lines.
Claim 5
Dependent Claim
293 words
A solid state peripheral storage device for receiving a plurality of address signals supplied on an address bus, an address control signal and a control signal, said device for providing 2N data signals simultaneously on 2N data signal lines, or N data signals simultaneously on one group of N contiguous data signal lines; said device comprising: a plurality of even number of substantially identical semiconductor memory integrated circuit chips, divided into two groups; each chip comprising: an addressable memory circuit for providing N data signals simultaneously on two N/2 internal data signal lines in response to the address signals supplied on the address bus; multiplexer means for receiving the N data signals on the two N/2 internal data signal lines, the control signal and the address control signal and for providing: N data signals simultaneously on two N/2 external data signal lines in response to the control signal being in one state; or a first collection of N/2 data signals from one of the two N/2 internal data signal lines to one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in one state; a second collection of N/2 data signals from another of the two N/2 internal data signal lines to said one of the two N/2 external data signal lines in response to the control signal being in another state and the address control signal being in another state; means for grouping said one of the two N/2 external data signal lines of one group of memory chips with said one of the two N/2 external data signal lines of another group of memory chips to form the one group of N contiguous data signal lines.
Claim 6
Dependent Claim
20 words
The device of claim 3 wherein each memory circuit of each chip comprises an array of electrically alterable programmable cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |