Method for manufacturing a semiconductor integrated circuit device

Claim 1

A method of manufacturing a semiconductor integrated circuit device having a series gate matrix in which insulated-gate field effect transistors are arranged in rows and columns and are serially connected to each other in each row, including the steps of: (a) forming an insulating layer on the surface of a semiconductor substrate of a first conductivity type, said insulating layer having a plurality of substantially parallel slots forming relatively thin insulating film, and relatively thick insulating film between adjacent slots, said slots extending along a row direction; (b) forming a conductive film over said substrate; (c) selectively forming a resist pattern on said conductive film along a column direction being substantially perpendicular to said slots; (d) selectively forming a plurality of gate electrodes using said resist pattern; (e) introducing an impurity of said first conductivity type into said semiconductor substrate through said relatively thick insulating film using said resist patterns and said gate electrodes as masks between said gate electrodes to form a channel stopper diffusion layer beneath said relatively thick insulating film to increase the impurity concentration of the first conductivity type; (f) selectively forming a plurality of masking layers over said substrate; and (g) introducing an impurity of a second conductivity type into said semiconductor substrate so as to activate areas under said gate electrodes and said relatively thin insulating film using said masking layers and said relatively thick insulating film as masks.

Claim 2

A method of manufacturing a semiconductor integrated circuit device having a series gate matrix in which insulated-gate field effect transistors are arranged in rows and columns and are serially connected to each other in each row, including the steps of: (a) forming an insulating layer on the surface of a semiconductor substrate of a first conductivity type, said insulating layer having a plurality of substantially parallel slots forming relatively thin insulating film, and relatively thick insulating film between adjacent slots, said slots extending along a row direction; (b) forming a conductive film over said substrate; (c) selectively forming a resist pattern on said conductive film along a column direction being substantially perpendicular to said slots; (d) selectively forming a plurality of gate electrodes using said resist pattern; (e) introducing an impurity of said first conductivity type into said semiconductor substrate through said relatively thick insulating film using said resist patterns and said gate electrodes as masks between said gate electrodes to form a channel stopper diffusion layer beneath said relatively thick insulating film to increase the impurity concentration of the first conductivity type; (f) selectively forming a plurality of masking layers over said substrate; and (g) introducing an impurity of a second conductivity type into said semiconductor substrate so as to activate areas under said gate electrodes and said relatively thin insulating film using said masking layers and said relatively thick insulating film as masks.