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US5371869A Expired / Lapsed US ⏱️ 0.0 years remaining

Micro-controller unit for selectively accessing an internal memory or an external extended memory using a read/write terminal

Assignee: Samsung Electronics Co Ltd
•
Filing: 1992-01-03
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Granted: 1994-12-06
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Expires: 2012-01-03
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Abstract

Abstract A micro-controller unit (MCU) selectively accesses one of an external extended memory and an internal memory in response to a signal on a read/write terminal instead of an additional terminal. The micro-controller unit includes an external memory control block, an external timing control block, and the internal memory, and additionally includes a reset detection circuit, a memory access clock generation circuit and a latch. The reset detection circuit receives an external reset signal for initializing the MCU and an external clock, and detects whether the micro-controller unit is reset. The memory access clock generation circuit receives an output signal from the reset detection circuit and generates a memory access clock signal to selectively access one of the internal memory and the external extended memory. The latch receives the external reset signal, the memory access clock signal and a memory interface signal applied to the read/write terminal for applying a memory access selection signal to the external memory control block, the external timing control block and the internal memory, whereby a memory selection is performed by the reset signal and the memory interface signal.

Inventors

  • 👤 Byeongjun Lee

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:39
CPC Classifications
G; G11; G11B; G11B13/00; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 147 words
In a micro-controller unit for selectively accessing an external extended memory and including an external memory control block, an external timing control block, and an internal memory, an improvement comprising: a reset detection circuit receiving an external reset signal for initializing said micro-controller unit and an external clock, and for detecting whether the micro-controller unit is reset; a memory access clock generation circuit receiving an output signal from said reset detection circuit and generating a memory access clock signal to selectively access one of the internal memory and the external extended memory; and a latch receiving said memory access clock signal, said external reset signal and a memory interface signal, for applying a memory access selection signal to said external memory control block, said external timing control block and said internal memory, whereby a memory selection is performed by said reset signal and said memory interface signal.
Claim 2
Dependent Claim 147 words
In a micro-controller unit for selectively accessing an external extended memory and including an external memory control block, an external timing control block, and an internal memory, an improvement comprising: a reset detection circuit receiving an external reset signal for initializing said micro-controller unit and an external clock, and for detecting whether the micro-controller unit is reset; a memory access clock generation circuit receiving an output signal from said reset detection circuit and generating a memory access clock signal to selectively access one of the internal memory and the external extended memory; and a latch receiving said memory access clock signal, said external reset signal and a memory interface signal, for applying a memory access selection signal to said external memory control block, said external timing control block and said internal memory, whereby a memory selection is performed by said reset signal and said memory interface signal.
Claim 3
Dependent Claim 16 words
The improvement according to claim 1, wherein said reset memory interface signal comprises a read/write signal.
Claim 4
Dependent Claim 62 words
The improvement according to claim 1, wherein said reset detection circuit includes: a plurality of D-type flip-flops, each supplied in common with an external clock signal, for generating sequentially delayed signals in response to a signal level-change of said external reset signal; and an AND gate responsive to an output of each of said D-type flip-flops for generating a system reset signal.
Claim 5
Dependent Claim 31 words
The improvement according to claim 1, wherein said memory access clock generation circuit comprises an AND gate coupled to receive a plurality of sequentially delayed inputs from said reset detection circuit.
Claim 6
Dependent Claim 42 words
The improvement according to claim 1, wherein said latch includes a metal oxide semiconductor (MOS) transistor switched ON by a high level of said memory access clock signal and a gate latched by a read/write signal when said MOS transistor is ON.

References Cited (Backward Citations)

US4432049A Cited
US4542453A Cited
US4677586A Cited
US4870562A Cited
US4870563A Cited
US5046180A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-12-05 1998-06-06 1998-12-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-12-05 2002-06-06 2002-12-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-12-05 2006-06-06 2006-12-06 $7700.00 Window Closed / Lapsed

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