US4870563A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information processing apparatus having a mask function
Assignee: NEC Electronics Corp
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Filing: 1987-04-08
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Granted: 1989-09-26
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Expires: 2007-04-08
Abstract
Abstract An information processing apparatus having a mask operation includes a first circuit generating a first mask control signal indicating a start bit position of a data to be processed and a second circuit generating a second mask control signal indicating an end bit position of that data. The first mask control signal and the second mask control signal are applied to a gate circuit by which a non-mask signal is produced for a bit or bits from the start bit position to the end bit position and a mask signal is produced for the other bit or bits.
Inventors
- 👤 Tetsuji Oguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:18
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/764; G06F7/38; G06F7/48; G06F7/57
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
178 words
An information processing apparatus comprising: a memory from which a fixed plural number of bits are read out at the same time in one read operation; an arithmetic unit coupled to the memory and performing an arithmetic operation on a part of the bits read out of said memory, said part being not masked by a mask signal; and a mask signal producing circuit means producing said mask signal for masking at least one bit among the bits read out of said memory, said mask signal producing circuit means comprising: a first means for generating first mask control signals consisting of said fixed number of bits, which represent a start bit position from which the arithmetic operation starts, a second means for generating second mask control signals consisting of said fixed number of bits, which represent an end bit position at which said arithmetic operation is terminated, and a third means coupled to said first means and said second means for producing said mask signal according to said first mask control signals and said second mask control signals.
Claim 2
Dependent Claim
178 words
An information processing apparatus comprising: a memory from which a fixed plural number of bits are read out at the same time in one read operation; an arithmetic unit coupled to the memory and performing an arithmetic operation on a part of the bits read out of said memory, said part being not masked by a mask signal; and a mask signal producing circuit means producing said mask signal for masking at least one bit among the bits read out of said memory, said mask signal producing circuit means comprising: a first means for generating first mask control signals consisting of said fixed number of bits, which represent a start bit position from which the arithmetic operation starts, a second means for generating second mask control signals consisting of said fixed number of bits, which represent an end bit position at which said arithmetic operation is terminated, and a third means coupled to said first means and said second means for producing said mask signal according to said first mask control signals and said second mask control signals.
Claim 3
Dependent Claim
61 words
An apparatus as claimed in claim 1, wherein said first mask control signals generated from said first means contain 1st to Nth bits in which the i-th (1≦i≦N) bit represents the start bit position and said second mask control signals generated from said second means contain 1st to Nth bits in which the j-th (1≦j≦N) bit represents the end bit position.
Claim 4
Dependent Claim
113 words
An apparatus as claimed in claim 2, wherein each of said 1st bit to (i-1)-th bit of said first mask control signals is a first logic level signal, each of said i-th bit to Nth bit of said first mask control signals being a second logic level signal, each of said 1st bit to j-th bit of said second mask control signals being said second logic level signal, and each of said (j+1)-th bit to N-th bit of said second mask control signals being said first logic level signal, said third means producing the mask signal corresponding to said 1st bit to said (i-1)th bit and said (j+1)-th bit to said Nth bit.
Claim 5
Dependent Claim
36 words
An apparatus as claimed in claim 1, wherein said first means has a first table memory storing said first mask control signals, said second means having a second table memory storing said second mask control signals.
Claim 6
Independent Claim
180 words
An apparatus having a mask function for masking at least one bit among 1st to n-th bits comprising a first means for generating simultaneously first data consisting of X 1 to X n signals in which X 1 to X i-1 signals have a first logic and X i to X n signals have a second logic, a second means for generating simultaneously second data consisting of Y 1 to Y n signals in which Y 1 to Y j signals have said second logic and Y j+1 to Y n signals have said first logic, X i representing a start position of a bit portion not to be masked, Y j representing an end position of said bit portion not to be masked, and means coupled to said first means and said second means for producing simultaneously a mask signal for the 1st to (i-1) th bits and (j+1)-th to n-th bits and a non-mask signal for the i-th to j-th bits according to said X 0 to X.sub. n signals and said Y 0 to Y n signals.
Claim 7
Independent Claim
180 words
An apparatus having a mask function for masking at least one bit among 1st to n-th bits comprising a first means for generating simultaneously first data consisting of X 1 to X n signals in which X 1 to X i-1 signals have a first logic and X i to X n signals have a second logic, a second means for generating simultaneously second data consisting of Y 1 to Y n signals in which Y 1 to Y j signals have said second logic and Y j+1 to Y n signals have said first logic, X i representing a start position of a bit portion not to be masked, Y j representing an end position of said bit portion not to be masked, and means coupled to said first means and said second means for producing simultaneously a mask signal for the 1st to (i-1) th bits and (j+1)-th to n-th bits and a non-mask signal for the i-th to j-th bits according to said X 0 to X.sub. n signals and said Y 0 to Y n signals.
Claim 8
Dependent Claim
64 words
An apparatus as claimed in claim 5, wherein said producing means has 1st to n-th gate means, each gate means receiving the corresponding X signal and Y signal and producing the non-mask signal when X signal and Y signal are both said second logics and the mask signal when at least one of the X signal and the Y signal is said first logic.
Claim 9
Dependent Claim
33 words
An apparatus as claimed in claim 5, wherein said X 0 to X n signals and said Y 0 to Y n signals are applied to said producing means at the same time.
Claim 10
Independent Claim
150 words
An apparatus producing a mask signal and a non-mask signal for a plurality of bits read out of a memory comprising a first means for generating a first data indicating a start bit position from which processing starts, a second means for generating second data indicating an end bit position at which said processing is terminated, a third means coupled to said first means and said second means for activating said first means and said second means according to a start bit address designating said start bit position and an end bit address designating said end bit position, and a fourth means coupled to said first means and said second means for producing the mask signal for a part of said bits not to be processed and the non-mask signal for the remaining part of said bits to be processed according to said first data and said second data, respectively.
Claim 11
Independent Claim
150 words
An apparatus producing a mask signal and a non-mask signal for a plurality of bits read out of a memory comprising a first means for generating a first data indicating a start bit position from which processing starts, a second means for generating second data indicating an end bit position at which said processing is terminated, a third means coupled to said first means and said second means for activating said first means and said second means according to a start bit address designating said start bit position and an end bit address designating said end bit position, and a fourth means coupled to said first means and said second means for producing the mask signal for a part of said bits not to be processed and the non-mask signal for the remaining part of said bits to be processed according to said first data and said second data, respectively.
Claim 12
Dependent Claim
47 words
An apparatus as claimed in claim 8, further comprising a fifth means receiving said start bit address and data representing a bit length of bits to be processed for producing said end bit address according to said start bit address and said data representing the bit length.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |