US3665175A
Expired / Lapsed
US
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Dynamic storage address blocking to achieve error toleration in the addressing circuitry
Assignee: International Business Machines Corp
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Filing: 1968-09-03
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Granted: 1972-05-23
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Expires: 1988-09-03
Abstract
Abstract Mapping control means for achieving error toleration in computer addressing circuitry including switching means for connecting an address register with the effective address register of a basic operating module. The switching means are operable by a blocking register and at least one status register to control the mapping connections in a given manner. The invention is characterized by the provision of an address blocking register and a mask register that process a sequence of failed addresses and insert corresponding control instructions in the blocking and status registers so that the switching means dynamically excludes access to the memory area affected by the faulty address circuitry.
Inventors
- 👤 Willard G Bouricius
- 👤 William C Carter
- 👤 John P Roth
- 👤 Peter R Schneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:34
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
153 words
Address mapping means for achieving error toleration in the addressing circuitry of a computer system including an address register (AR) and an effective address register (ER) for transmitting address information to a basic operating module, comprising switching means connecting said address register (AR) with said effective address register (ER); means including a blocking register (B) and at least one status register (S) for controlling said switching means to map the address bits supplied to said effective address register in a controlled manner, the number of said status registers corresponding to the number of entries in said blocking register; and means including an address blocking register (ABR) and a mask register (MR) adapted for processing a sequence of failed addresses and for inserting control instructions in said blocking and status registers to control the mapping of said switching means to dynamically exclude access to a memory area affected by faults in the addressing circuitry.
Claim 2
Dependent Claim
153 words
Address mapping means for achieving error toleration in the addressing circuitry of a computer system including an address register (AR) and an effective address register (ER) for transmitting address information to a basic operating module, comprising switching means connecting said address register (AR) with said effective address register (ER); means including a blocking register (B) and at least one status register (S) for controlling said switching means to map the address bits supplied to said effective address register in a controlled manner, the number of said status registers corresponding to the number of entries in said blocking register; and means including an address blocking register (ABR) and a mask register (MR) adapted for processing a sequence of failed addresses and for inserting control instructions in said blocking and status registers to control the mapping of said switching means to dynamically exclude access to a memory area affected by faults in the addressing circuitry.
Claim 3
Dependent Claim
25 words
Apparatus as defined in claim 1, wherein each member of said sequence of failed addresses is handled one at a time as it is detected.
Claim 4
Dependent Claim
57 words
Apparatus as defined in claim 2 wherein said address blocking register (ABR) is adapted to contain the logical AND of said sequence of failed addresses, and further wherein said mask register (MR) is operable to effect comparison of only those bits of the address blocking register (ABR) that correspond with bits contaiNing 1''s in the mask register.
Claim 5
Dependent Claim
36 words
Apparatus as defined in claim 3, and further including means for inserting in said blocking register (B) the bits in the address blocking register (ABR) that correspond with those bits containing 1''s in the mask register.
Claim 6
Dependent Claim
40 words
Apparatus as defined in claim 4, and further including means responsive to the introduction of the first failed address supplied to said address blocking register (ABR) for setting 1''s in each of the bit positions of the mask register (MR).
Claim 7
Dependent Claim
52 words
Apparatus as defined in claim 5, wherein the number of status registers is i; and further including means for inserting 1''s into the ith status register up to and including the bit position of the ith 1 in said mask register, the remaining bit positions of said ith status register containing 0''s.
Claim 8
Dependent Claim
96 words
Apparatus as defined in claim 5, wherein the number of status registers and blocking register entries is two; and further including means for setting both status registers to all 0''s, means for determining the location of the first 1 in the mask register, means for setting to 1''s the bit position of said status registers up to and including the location of said first one in the mask register, and means for inserting in the first entry of the blocking register (B1) the bit present in the address blocking register ABR at the corresponding bit location.
Claim 9
Dependent Claim
94 words
Apparatus as defined in claim 7, and further including means for locating the position of the second ''''1'''' in said mask register, means for setting to ''''1''s'''' all the bit positions in said second status register up to and including the bit position corresponding to the position of the second ''''1'''' in said mask register, the remaining positions in said second status register being 0''s, and means for inserting in the second blocking register (B2) the bit in said address blocking register corresponding to the position of the second ''''1'''' in said mask register.
Claim 10
Dependent Claim
42 words
Apparatus as defined in claim 5, and further including means responsive to the introduction of a subsequent failed address supplied to said address blocking register (ABR) for ANDING the subsequent failed address with the prior contents of the address blocking register (ABR).
Claim 11
Dependent Claim
41 words
Apparatus as defined in claim 9, and further including means for ANDING with the old value in the mask register (MR) the complement of the old value in the address blocking register (ABR) and the Exclusive-OR of the subsequent failed address.
Claim 12
Dependent Claim
203 words
Apparatus as defined in claim 5, and further including means for testing the contents of said mask register, comprising a plurality of normally disabled first gates (146) associated with the bits of said mask register, respectively; mask register counter means for successively enabling said first gates, respectively; a pair of OR circuits (152, 154) each having inputs connected with each of said first gates, respectively; a pair of first AND circuits (202,204) each having first inputs connected with the outputs of one of said OR circuits (152); means including an inverter circuit (210) connecting a second input of one of said AND circuits (204) with the right hand line (208) of said mask register counter, the other AND circuit (202) being directly connected with said right hand line; a normally disabled second gate (156) having three inputs connected with the outputs of said AND circuits and the output of the other of said OR circuits (154), respectively, said second gate having three output lines that are activated, respectively, when the tested bit in the mask register is a ''''0'''' and not the right hand bit, a ''''1'''', and a ''''0'''' that is the right-hand bit; and means (CL4) for enabling said second gate.
Claim 13
Dependent Claim
78 words
AppaRatus as defined in claim 11, and further including a third OR circuit (162) having a pair of inputs connected with the outputs of said pair of OR circuits, respectively; and a plurality of second AND circuits (148) having outputs connected with the bits of said status register (S1), respectively, said AND circuits having first inputs connected with the output of said third OR circuit, and second inputs connected for successive actuation by said mask register counter means.
Claim 14
Dependent Claim
54 words
Apparatus as defined in claim 12, and further including a third AND circuit (160) connected between said third OR circuit (162) and said second AND circuits (148), and means (158) for enabling said third AND gate when the tested bit in the mask register is other than a 0 in the right hand bit.
Claim 15
Dependent Claim
16 words
Apparatus as defined in claim 13, and further including means for incrementing said mask register counter.
Claim 16
Dependent Claim
32 words
Apparatus as defined in claim 14, wherein said counter incrementing means includes means (CL5) responsive to a zero in the tested bit of the mask register other than the right hand bit.
Claim 17
Dependent Claim
66 words
Apparatus as defined in claim 14, and further including a second status register (S2); a plurality of fourth AND circuits (150) having outputs connected with the bits of said second status register (S2), respectively, said fourth AND circuits having inputs connected with the output of said third OR circuit (162), and means connecting said fourth AND circuits for successive operation by said mask register counter means.
Claim 18
Dependent Claim
56 words
Apparatus as defined in claim 14, and further including fifth AND circuit means (166) connected between said fourth AND circuit means (150) and said third OR circuit (162), and means (164) for enabling said fifth AND circuit means when the bit being tested in the mask register is other than a 0 in the right-hand bit.
Claim 19
Dependent Claim
81 words
Apparatus as defined in claim 17, wherein said means for opening said fifth AND circuit means further includes a normally disabled third gate (170) having inputs connected with the inputs of said second gate, respectively, said third gate having three output lines that are activated, respectively, when the tested bit in the mask register is a ''''0'''' and not the right hand bit, a ''''1'''', and a ''''0'''' that is the right-hand bit; and means (CL14) for enabling said third gate.
Claim 20
Dependent Claim
92 words
Apparatus as defined in claim 14, and further including a plurality of normally disabled fourth gate means (142) associated with said address blocking register (ABR), respectively, and successively enabled by said mask register counter means; fourth OR circuit means having inputs connected with the outputs of said fourth gate means, respectively; a normally disabled fifth gate (174) connecting the output of said OR circuit means with the blocking register; and means (CL7) for enabling said fifth gate when a 1 is present in the bit being tested in said mask register means.
Claim 21
Dependent Claim
165 words
Apparatus as defined in claim 14, and further including ADDF register means for receiving a failed address that is to be blocked; first and second hold register means (HOLD 1, HOLD 2); normally disabled sixth and seventh gate means (198, 192) for connecting the output of said hold register means with the inputs of said mask register and said address blocking register, respectively; a plurality of sixth AND circuit means (182) having outputs connected with the inputs, respectively, of said first hold register means; means including a normally disabled eighth gate (180) and fifth OR circuit means for connecting the bits of the address blocking register (ABR) with one input of each of said sixth AND circuit means, respectively; means including normally disabled ninth gate means (178) and sixth OR circuit means for connecting the bits of the ADDF register with the other inpUts of said sixth AND circuit means; and means (CL12, CL10, CL8) for enabling said sixth, seventh, eighth and ninth gate means.
Claim 22
Dependent Claim
40 words
Apparatus as defined in claim 20, and further including normally disabled 10th gate means (194) for connecting the bits of said mask register with said sixth OR circuit means, respectively; and means (CL 11) for enabling said tenth gate means.
Claim 23
Dependent Claim
114 words
Apparatus as defined in claim 21, and further including a plurality of Exclusive-OR circuit means (188) associated with said second hold register means (HOLD 2); a plurality of inverter circuits (190) connecting the outputs of said Exclusive-OR circuit means with the inputs of said second hold register means, respectively; normally disabled 11th gate means (184) connecting one of the inputs of each of said Exclusive-OR circuit means with the bits of said ADDF register, respectively; normally disabled 12th gate means (186) connecting the other inputs of each of said Exclusive-OR means with the bits of said address blocking register (ABR) respectively; and means (CL 9) for enabling said 11th and 12th gate means, respectively.
Claim 24
Dependent Claim
30 words
Apparatus as defined in claim 22, and further including normally disabled thirteenth gate means (196) for connecting the bits of said second hold register with the fifth OR circuits, respectively.
Claim 25
Dependent Claim
87 words
Apparatus as defined in claim 4, wherein said switching means comprises a plurality of seventh OR circuits (300) the outputs of which are connected with the bits of said effective address register, respectively; a plurality of seventh AND circuits (302) the outputs of which are connected with the inputs of said seventh OR circuits, respectively, each of said seventh AND circuits having a first input connected with said blocking register, and a second input connected with the ''''1'''' output of the corresponding flip-flop of the status register.
Claim 26
Dependent Claim
71 words
Apparatus as defined in claim 24, wherein said switching means further includes a plurality of eighth AND circuit means (304) the outputs of which are connected with said seventh OR circuit, respectively, said eighth AND circuit means including first inputs connected with the corresponding bit position of said address register, and second inputs connected with the 0 outputs of the flip-flop of the corresponding bit positions of the status register, respectively.
Claim 27
Dependent Claim
64 words
Apparatus as defined in claim 25, wherein said switching means further includes a plurality of ninth AND circuit means (306) the outputs of which are connected with the inputs of at least some of said OR circuits, respectively, said ninth AND circuit means having first and second inputs connected with the flip-flops of the next bit positions of said address and status registers, respectively.
Claim 28
Dependent Claim
14 words
Apparatus as defined in claim 26, wherein said switching means include overcapacity indicating means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-23 | 1975-11-22 | 1976-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-23 | 1979-11-22 | 1980-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-23 | 1983-11-22 | 1984-05-23 | $7700.00 | Window Closed / Lapsed |