US5369039A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making charge coupled device/charge super sweep image system
Assignee: Texas Instruments Inc
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Filing: 1992-10-09
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Granted: 1994-11-29
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Expires: 2012-10-09
Abstract
Abstract Described is a new high performance CCD image sensor technology which can be used to build a versatile image senor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.
Inventors
- 👤 Jaroslav Hynecek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:48
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/70; H04N25/71; H04N25/713; H04N25/73; H04N25/745; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/153
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A method for fabricating an image sensor comprising: forming a semiconductor layer of a first conductivity type; forming a series of semiconductor wells of a second conductivity type in said semiconductor layer; growing a first insulator layer over said semiconductor layer; forming a semiconductor buried channel region of said first conductivity type in selected ones of said semiconductor wells; depositing a first polysilicon layer over the first insulator layer; depositing a patterned insulator over said first polysilicon layer above said buried channel region to define a series of charge transfer channels; forming a series of channel stop regions adjacent respective ones of said charge transfer channels; etching the first polysilicon layer to form a resistive gate over first portions of said buried channel region; depositing a patterned second polysilicon layer overlying and spaced apart from said resistive gate, and overlying and spaced apart from second portions of said buried channel region; and forming a virtual gate in said buried channel region below said resistive gate.
Claim 2
Independent Claim
165 words
A method for fabricating an image sensor comprising: forming a semiconductor layer of a first conductivity type; forming a series of semiconductor wells of a second conductivity type in said semiconductor layer; growing a first insulator layer over said semiconductor layer; forming a semiconductor buried channel region of said first conductivity type in selected ones of said semiconductor wells; depositing a first polysilicon layer over the first insulator layer; depositing a patterned insulator over said first polysilicon layer above said buried channel region to define a series of charge transfer channels; forming a series of channel stop regions adjacent respective ones of said charge transfer channels; etching the first polysilicon layer to form a resistive gate over first portions of said buried channel region; depositing a patterned second polysilicon layer overlying and spaced apart from said resistive gate, and overlying and spaced apart from second portions of said buried channel region; and forming a virtual gate in said buried channel region below said resistive gate.
Claim 3
Dependent Claim
37 words
The method of claim 1 wherein said forming of said series of channel stop regions includes implanting boron in portions of said first polysilicon layer overlaying said buried channel region and not covered by said patterned insulator.
Claim 4
Dependent Claim
16 words
The method of claim 1 wherein said step of forming said virtual gate includes implanting boron.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein said first conductivity type is n type.
Claim 6
Dependent Claim
13 words
The method of claim 1 wherein said second conductivity type is p type.
Claim 7
Dependent Claim
15 words
The method of claim 1 further comprising forming said semiconductor layer over a semiconductor substrate.
Claim 8
Dependent Claim
14 words
The method of claim 6 wherein said semiconductor substrate is an epitaxial semiconductor substrate.
Claim 9
Dependent Claim
15 words
The method of claim 6 wherein said semiconductor substrate is of said first conductivity type.
Claim 10
Dependent Claim
17 words
The method of claim 8 wherein said semiconductor substrate is more heavily doped than said semiconductor layer.
Claim 11
Dependent Claim
22 words
The method of claim 1 further comprising forming a plurality of CMOS transistors in said semiconductor layer adjacent said buried channel region.
References Cited (Backward Citations)
US3944850A
Cited
US4639940A
Cited
US4139784A
Cited
US4152606A
Cited
US4249145A
Cited
US4231810A
Cited
JPS5590124A
Cited
JPS56119994A
Cited
US4489423A
Cited
US4447735A
Cited
US4612521A
Cited
US4716580A
Cited
US4774586A
Cited
US4719448A
Cited
US4794279A
Cited
US4866496A
Cited
US5192990A
Cited
US4995061A
Cited
JPH01168113A
Cited
US4912560A
Cited
US5151386A
Cited
US5223725A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-28 | 2006-05-30 | 2006-11-29 | $7700.00 | Window Closed / Lapsed |