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US5367550A
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Break address detecting circuit
Assignee: Renesas Electronics Corp
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Filing: 1993-10-19
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Granted: 1994-11-22
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Expires: 2013-10-19
Abstract
Abstract A break address detecting circuit sets a breakpoint in debugging a program for microprocessor, a signal processor, or the like. A first register holds a stop address ADstp. A first counter is initialized by a reset signal and counts up clock pulses in synchronism with a clock signal indicative of an instruction execution cycle. A selector selects a program address when the program is debugged, or selects output data from the first counter in step-by-step operation. A first comparator outputs a comparison result signal CR which is of an active level when output data from the selector and output data from the first register agree with each other. A second counter is initialized by the reset signal and counts up the comparison result signal each time the comparison result signal is of an active level. A second register holds a stop count CVstp. A second comparator outputs a break signal of an active level when output data from the second counter and output data from the second register agree with each other.
Inventors
- 👤 Ryuji Ishida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
192 words
A break address detecting circuit comprising: first data holding means for holding and outputting first data of a predetermined value; first counter means initializable by a reset signal for counting up clock pulses in synchronism with a clock signal and outputting counted data; selector means for selecting and outputting in response to a selection signal either a program address or output data from said first counter means; first comparator means for comparing output data from said selector means and output data from said first data holding means and outputting a comparison result signal which is of an active level when the compared data agree with each other; second counter means initializable by said reset signal for counting up the comparison result signal each time the comparison result signal is of an active level and outputting counted data; second data holding means for holding and outputting second data of a predetermined value; and second comparator means for comparing output data from said second data holding means and output data from said second counter means and outputting a break signal which is of an active level when the compared data agree with each other.
Claim 2
Dependent Claim
192 words
A break address detecting circuit comprising: first data holding means for holding and outputting first data of a predetermined value; first counter means initializable by a reset signal for counting up clock pulses in synchronism with a clock signal and outputting counted data; selector means for selecting and outputting in response to a selection signal either a program address or output data from said first counter means; first comparator means for comparing output data from said selector means and output data from said first data holding means and outputting a comparison result signal which is of an active level when the compared data agree with each other; second counter means initializable by said reset signal for counting up the comparison result signal each time the comparison result signal is of an active level and outputting counted data; second data holding means for holding and outputting second data of a predetermined value; and second comparator means for comparing output data from said second data holding means and output data from said second counter means and outputting a break signal which is of an active level when the compared data agree with each other.
Claim 3
Dependent Claim
177 words
A break address detecting circuit comprising: first data holding means for holding and outputting first data of a predetermined value; first comparator means for comparing output data from said first data holding means and a program address and outputting a comparison result signal which is of an active level when the compared data and program address agree with each other; selector means for selecting in response to a selection signal either said comparison result signal or a clock signal which repeatedly alternates between active and inactive levels with predetermined timing; counter means initializable by a reset signal for counting output data from said selector means each time the output data from said selector means is of an active level and outputting counted data; second data holding means for holding and outputting second data of a predetermined value; and second comparator means for comparing output data from said second data holding means and output data from said counter means and outputting a break signal which is of an active level when the compared data agree with each other.
Claim 4
Dependent Claim
177 words
A break address detecting circuit comprising: first data holding means for holding and outputting first data of a predetermined value; first comparator means for comparing output data from said first data holding means and a program address and outputting a comparison result signal which is of an active level when the compared data and program address agree with each other; selector means for selecting in response to a selection signal either said comparison result signal or a clock signal which repeatedly alternates between active and inactive levels with predetermined timing; counter means initializable by a reset signal for counting output data from said selector means each time the output data from said selector means is of an active level and outputting counted data; second data holding means for holding and outputting second data of a predetermined value; and second comparator means for comparing output data from said second data holding means and output data from said counter means and outputting a break signal which is of an active level when the compared data agree with each other.
Claim 5
Dependent Claim
42 words
A break address detecting circuit according to claim 1, wherein said first data holding means comprises means for holding as said first data an address where a break is to occur, and said selector means comprises means for selecting a program address.
Claim 6
Dependent Claim
41 words
A break address detecting circuit according to claim 2, wherein said first data holding means for holding as said first data an address where a break is to occur, and said selector means comprises means for selecting said comparison result signal.
Claim 7
Dependent Claim
51 words
A break address detecting circuit according to claim 1, wherein said first data holding means comprises means for holding as said first data the number of instruction cycles executed after a program is started, and said selector means comprises means for selecting the counted data outputted from said first counter means.
Claim 8
Dependent Claim
38 words
A break address detecting circuit according to claim 2, wherein said second data holding means comprises means for holding the number of steps as said second data, and said selector means comprises means for selecting said clock signal.
Claim 9
Dependent Claim
39 words
A break address detecting circuit according to claim 1, further comprising means for resetting the data stored in said second data holding means by adding "1" to the data which has been stored in said second data holding means.
Claim 10
Dependent Claim
23 words
A break address detecting circuit according to claim 1, further comprising means for setting said first counter means to the number of steps.
Claim 11
Dependent Claim
39 words
A break address detecting circuit according to claim 2, further comprising means for resetting the data stored in said second data holding means by adding "1" to the data which has been stored in said second data holding means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |