Semiconductor memory device

Claim 2

A semiconductor memory device comprising: source voltage supplying means for receiving an external source voltage and supplying a first source voltage corresponding to the external source voltage and a second source voltage lower than the first source voltage to an internal circuit, said source voltage supplying means including, converting means for converting the external source voltage to the second source voltage, and source voltage selecting means for selecting one of the second source voltage obtained by the converting means and the first source voltage corresponding to the external source voltage; a memory cell array section, including at least a sense amplifier, to which the first source voltage is supplied during a first operation in which data is transferred between said memory cell array section and an external device, and to which the second source voltage is supplied during a second operation in which data is refreshed and maintained in said memory cell array section, wherein said source voltage selecting means selects in accordance with the first or the second operation of the memory cell array section; and a peripheral circuit to which the first source voltage is supplied during the second operation in which the second source voltage is supplied to said memory cell array section to refresh and maintain data.

Claim 3

A semiconductor memory device according to claim 1, wherein said source voltage selecting means includes switching means for switching the first source voltage and the second source voltage upon receipt of a command signal supplied from an external circuit.

Claim 4

A semiconductor memory device according to claim 1, wherein said converting means comprises: first source voltage converting means for receiving and converting the external source voltage to a first internal source voltage which is lower than the external source voltage; and second source voltage converting means for receiving and converting the external source voltage to a second internal source voltage which is lower than the first internal source voltage obtained by said first source voltage converting means.

Claim 5

A semiconductor memory device according to claim 1, wherein said converting means comprises: source voltage lowering means for receiving and lowering the external source voltage and supplying the lowered voltage to the internal circuit; reference potential generating means for generating first and second reference potentials; and reference potential supplying means for supplying the first reference potential to the source voltage lowering means when the first source voltage is to be used as an operation voltage, and the second reference potential to the source voltage lowering means when the second source voltages is to be used as an operation voltage.

Claim 6

A semiconductor memory device according to claim 1, wherein said peripheral circuit includes at least an address buffer and a data input/output buffer.

Claim 7

A semiconductor memory device according to claim 1, wherein said peripheral circuit includes an address buffer, a data input/output buffer, a row decoder, and a column decoder.

Claim 8

A semiconductor memory device comprising: a memory cell array section including a plurality of memory cells and which is powered in accordance with potentials derived from a memory cell array section voltage; peripheral circuitry including circuitry for decoding address data to select said memory cells and which is powered in accordance with potentials derived from a peripheral circuitry voltage; means for supplying a first voltage to said peripheral circuitry as said peripheral circuitry voltage when said semiconductor memory device is in a first operating state in which said memory cell array section is accessed for data reading and writing, and for supplying said first voltage to said peripheral circuitry as said peripheral circuitry voltage when said semiconductor memory device is in a second operating state in which said memory cell array section is not accessed for data reading and writing; and a switch responsive to a first control signal for supplying said first voltage to said memory cell array section as said memory cell array section voltage when said semiconductor memory device is in said first operating state, and for supplying a second voltage lower than said first voltage to said memory cell array section as said memory cell array section voltage when said semiconductor memory device is in said second operating state.

Claim 9

A semiconductor memory device comprising: a memory cell array section including a plurality of memory cells and which is powered in accordance with potentials derived from a memory cell array section voltage; peripheral circuitry including circuitry for decoding address data to select said memory cells and which is powered in accordance with potentials derived from a peripheral circuitry voltage; means for supplying a first voltage to said peripheral circuitry as said peripheral circuitry voltage when said semiconductor memory device is in a first operating state in which said memory cell array section is accessed for data reading and writing, and for supplying said first voltage to said peripheral circuitry as said peripheral circuitry voltage when said semiconductor memory device is in a second operating state in which said memory cell array section is not accessed for data reading and writing; and a switch responsive to a first control signal for supplying said first voltage to said memory cell array section as said memory cell array section voltage when said semiconductor memory device is in said first operating state, and for supplying a second voltage lower than said first voltage to said memory cell array section as said memory cell array section voltage when said semiconductor memory device is in said second operating state.

Claim 10

The semiconductor memory device according to claim 7, wherein said memory cell array section further includes: pairs of bit lines to which said plurality of memory cells are connected, a plurality of word lines for selecting said memory cells, and sense amplifiers coupled to said pairs of bit lines.

Claim 11

The semiconductor memory device according to claim 8, further comprising: a first transfer transistor having a first terminal connected to said switch, a second terminal connected to a node common to first ones of said sense amplifiers, and a gate supplied with a second control signal.

Claim 12

The semiconductor memory device according to claim 9, further comprising: a second transfer transistor having a first terminal connected to a V ss potential, a second terminal connected to a node common to second ones of said sense amplifiers, and a gate supplied with a third control signal.

Claim 13

The semiconductor memory device according to claim 10, wherein said second transfer transistor is of a conductivity type opposite to a conductivity type of said first transfer transistor and said third control signal is complementary to said second control signal.

Claim 14

The semiconductor memory device according to claim 8, wherein said peripheral circuitry comprises: a column decoder for selecting said pairs of bit lines; and a row decoder for selecting said word lines.

Claim 15

The semiconductor memory device according to claim 7, further comprising: a voltage converting circuit for converting said first voltage to said second voltage and supplying said second voltage to said switch.

Claim 16

The semiconductor memory device according to claim 7, said memory cells each comprise a transfer transistor and a data storage capacitor.

Claim 17

The semiconductor memory device according to claim 14, wherein said memory cell array section further comprises: precharging circuitry for precharging said pairs of bit lines; and means for supplying a plate potential to said data storage capacitors.

Claim 18

The semiconductor memory device according to claim 7, wherein said second voltage is approximately one-half of said first voltage.

Claim 19

A semiconductor memory device comprising: a source voltage converting circuit for receiving an external voltage corresponding to a first source voltage and converting the external source voltage to a second source voltage lower than the first source voltage; a selection circuit which receives the first source voltage and the second source voltage for selecting one of the first source voltage and the second source voltage; a memory cell array section having a sense amplifier, said selection circuit supplying the first source voltage to said sense amplifier during a data transfer operation in which data is transferred between said memory cell array section and an external device, and said selection circuit supplying the second source voltage to said sense amplifier during a data refresh operation in which data in the memory cell array section is refreshed; and a peripheral circuit which receives the first source voltage during the data refresh operation.

Claim 20

A semiconductor memory device comprising: a source voltage converting circuit for receiving an external voltage corresponding to a first source voltage and converting the external source voltage to a second source voltage lower than the first source voltage; a selection circuit which receives the first source voltage and the second source voltage for selecting one of the first source voltage and the second source voltage; a memory cell array section having a sense amplifier, said selection circuit supplying the first source voltage to said sense amplifier during a data transfer operation in which data is transferred between said memory cell array section and an external device, and said selection circuit supplying the second source voltage to said sense amplifier during a data refresh operation in which data in the memory cell array section is refreshed; and a peripheral circuit which receives the first source voltage during the data refresh operation.