US5367486A
Expired / Lapsed
US
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Semiconductor memory device capable of correctly and serially reading stored data signals
Assignee: Mitsubishi Electric Corp
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Filing: 1991-09-26
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Granted: 1994-11-22
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Expires: 2011-09-26
Abstract
Abstract In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.
Inventors
- 👤 Junji Mori
- 👤 Takayuki Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1051
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
256 words
A semiconductor memory device comprising: a memory cell train including a plurality of memory cells arranged in at least one direction; a plurality of data bit holding means coupled to said memory cell train for holding data bit signals read from said plurality of memory cells, respectively; a serial bus line for serially transmitting the data bit signals held in said plurality of data bit holding means to the outside; serial selector means responsive to an externally applied clock signal for serially selecting the data bit signals to be provided therefrom to the outside; serial supply means responsive to said serial selector means for serially supplying the data bit signals held in said plurality of data bit holding means to said serial bus line; holding stabilizing means connected to said plurality of data bit holding means for stabilizing a signal holding function by said plurality of data bit holding means; and a plurality of sense amplifiers connected to said plurality of memory cells for sensing data from a memory cell and amplifying small voltage differences between pairs of bit lines; said plurality of data bit holding means receiving the data bit signals from said plurality of sense amplifiers and holding the data bit signals as potential levels of predetermined nodes therein; said serial supply means connected between said predetermined nodes and said serial bus line for separating and connecting said predetermined nodes from and to said serial bus line in accordance with said serial selector means; and said holding stabilizing means connected to said predetermined nodes.
Claim 2
Dependent Claim
256 words
A semiconductor memory device comprising: a memory cell train including a plurality of memory cells arranged in at least one direction; a plurality of data bit holding means coupled to said memory cell train for holding data bit signals read from said plurality of memory cells, respectively; a serial bus line for serially transmitting the data bit signals held in said plurality of data bit holding means to the outside; serial selector means responsive to an externally applied clock signal for serially selecting the data bit signals to be provided therefrom to the outside; serial supply means responsive to said serial selector means for serially supplying the data bit signals held in said plurality of data bit holding means to said serial bus line; holding stabilizing means connected to said plurality of data bit holding means for stabilizing a signal holding function by said plurality of data bit holding means; and a plurality of sense amplifiers connected to said plurality of memory cells for sensing data from a memory cell and amplifying small voltage differences between pairs of bit lines; said plurality of data bit holding means receiving the data bit signals from said plurality of sense amplifiers and holding the data bit signals as potential levels of predetermined nodes therein; said serial supply means connected between said predetermined nodes and said serial bus line for separating and connecting said predetermined nodes from and to said serial bus line in accordance with said serial selector means; and said holding stabilizing means connected to said predetermined nodes.
Claim 3
Dependent Claim
110 words
The semiconductor memory device according to claim 1, wherein said serial supply means includes a plurality of switching means responsive to said serial selection means for sequentially connecting between said plurality of data bit holding means and said serial bus line; each of said plurality of data bit holding means has a tendency to change the held data bit signals in response to the ON state of corresponding one of said switching means; and said holding stabilizing means includes a plurality of change prevention means connected to said plurality of data bit holding means, respectively, for preventing change in the data bit signals held in respective data bit holding means.
Claim 4
Dependent Claim
58 words
The semiconductor memory device according to claim 2 further comprising a plurality of bit lines connected to each of said plurality of memory cells for transmitting the data bit signals stored in respective memory cells, wherein said plurality of data bit holding means include a plurality of latch circuit means coupled to said plurality of bit lines, respectively.
Claim 5
Dependent Claim
69 words
The semiconductor memory device according to claim 3, wherein said plurality of change prevention means includes a plurality of capacitance means connected to said respective latch circuit means; and each of said capacitance means has a capacitance value determined by an operation speed required in said semiconductor memory device and a capability of said respective latch circuit means to be inverted by discharge of said serial bus line therethrough.
Claim 6
Dependent Claim
74 words
The semiconductor memory device according to claims 4, wherein each of said latch circuit means includes two inverter means coupled to said plurality of bit lines, respectively, and cross coupled to each other; and each of said capacitance means has a capacitance value determined by an operation speed required in said semiconductor memory device and a capability of said respective latch circuit means to be inverted by discharge of said serial bus line therethrough.
Claim 7
Dependent Claim
18 words
The semiconductor memory device according to claim 1, wherein said semiconductor memory device includes a field memory device.
Claim 8
Dependent Claim
237 words
A semiconductor memory device capable of serially reading stored data bit signals comprising: a memory cell train including a plurality of memory cells arranged in at least one direction; a plurality of bit lines connected to said plurality of memory cells, respectively; a plurality of latch circuits connected to said plurality of bit lines, respectively, for latching data a bit signals applied from said plurality of memory cells to respective bit lines during read operation; a serial bus line for serially transmitting the data bit signals latched in said plurality of latch circuits to the outside; a serial selector circuit responsive to an externally applied clock signal for serially selecting data bit signals to be read therefrom to the outside; a plurality of switching transistors connected between said plurality of latch circuits and said serial bus line, responsively, to an output signal generated from said serial selector circuit for sequentially turning on; said plurality of latch circuits having a tendency to change a latched signal with a potential on said serial bus line in response to the ON state of said plurality of switching transistors; and a plurality of capacitors connected to a plurality of connection nodes connecting said plurality of latch circuits and said plurality of switching transistor, respectively; said plurality of capacitors preventing the signals latched in said plurality of latch circuits from being changed by the ON state of said plurality of switching transistors.
Claim 9
Dependent Claim
237 words
A semiconductor memory device capable of serially reading stored data bit signals comprising: a memory cell train including a plurality of memory cells arranged in at least one direction; a plurality of bit lines connected to said plurality of memory cells, respectively; a plurality of latch circuits connected to said plurality of bit lines, respectively, for latching data a bit signals applied from said plurality of memory cells to respective bit lines during read operation; a serial bus line for serially transmitting the data bit signals latched in said plurality of latch circuits to the outside; a serial selector circuit responsive to an externally applied clock signal for serially selecting data bit signals to be read therefrom to the outside; a plurality of switching transistors connected between said plurality of latch circuits and said serial bus line, responsively, to an output signal generated from said serial selector circuit for sequentially turning on; said plurality of latch circuits having a tendency to change a latched signal with a potential on said serial bus line in response to the ON state of said plurality of switching transistors; and a plurality of capacitors connected to a plurality of connection nodes connecting said plurality of latch circuits and said plurality of switching transistor, respectively; said plurality of capacitors preventing the signals latched in said plurality of latch circuits from being changed by the ON state of said plurality of switching transistors.
Claim 10
Dependent Claim
18 words
The semiconductor memory device according to claim 7, wherein said semiconductor memory device comprises a field memory device.
Claim 11
Dependent Claim
153 words
A semiconductor memory device in accordance with claim 7, further comprising: a plurality of sense amplifiers connected to said plurality of memory cells for sensing data from a memory cell and amplifying small voltage differences between pairs of bit lines; said plurality of latch circuits receiving the data bit signals from said plurality of sense amplifiers and latching the data bit signals as potential levels of said plurality of connection nodes therein; said plurality of switching transistors connected between said connection nodes and said serial bus line for separating and connecting said connection nodes from and to said serial bus line in accordance with said serial selector circuit; and said plurality of capacitors connected to said connection nodes for discharging said serial bus line upon activation of said switching transistors thereby preventing change of the latched signal stored in said latch circuit by discharge of said serial bus line through said latch circuit.
Claim 12
Dependent Claim
249 words
A semiconductor memory device capable of serially reading stored data bit signals comprising: a memory cell train including a plurality of memory cells arranged in at least one direction; a plurality of bit lines connected to said plurality of memory cells, respectively; a plurality of latch circuits connected to said plurality of bit lines, respectively, for latching data bit signals applied from said plurality of memory cells to respective bit lines during read operation; a serial bus line for serially transmitting the data bit signals latched in said plurality of latch circuits to the outside; a serial selector circuit responsive to an externally applied clock signal for serially selecting the data bit signals to be read therefrom to the outside; a plurality of switching transistors connected between said plurality of latch circuits and said serial bus line, responsively, to an output signal generated from said serial selector circuit for sequentially turning on; said plurality of latch circuits having a tendency to change a latched signal with a potential on said serial bus line in response to the ON state of said plurality of switching transistors; and a plurality of capacitor means connected to a plurality of connection nodes connecting said plurality of latch circuits and said plurality of switching transistors for preventing change of a particular latched signal stored in a particular one of said plurality of latch circuits in response to discharge of said serial bus line through said particular latch circuit upon activation of said switching transistors.
Claim 13
Dependent Claim
249 words
A semiconductor memory device capable of serially reading stored data bit signals comprising: a memory cell train including a plurality of memory cells arranged in at least one direction; a plurality of bit lines connected to said plurality of memory cells, respectively; a plurality of latch circuits connected to said plurality of bit lines, respectively, for latching data bit signals applied from said plurality of memory cells to respective bit lines during read operation; a serial bus line for serially transmitting the data bit signals latched in said plurality of latch circuits to the outside; a serial selector circuit responsive to an externally applied clock signal for serially selecting the data bit signals to be read therefrom to the outside; a plurality of switching transistors connected between said plurality of latch circuits and said serial bus line, responsively, to an output signal generated from said serial selector circuit for sequentially turning on; said plurality of latch circuits having a tendency to change a latched signal with a potential on said serial bus line in response to the ON state of said plurality of switching transistors; and a plurality of capacitor means connected to a plurality of connection nodes connecting said plurality of latch circuits and said plurality of switching transistors for preventing change of a particular latched signal stored in a particular one of said plurality of latch circuits in response to discharge of said serial bus line through said particular latch circuit upon activation of said switching transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |