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US5367478A
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Mutual division circuit
Assignee: Sony Corp
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Filing: 1992-09-02
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Granted: 1994-11-22
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Expires: 2012-09-02
Abstract
Abstract A mutual division circuit which can reduce a circuit scale thereof considerably and which can also be operated at high speed to thereby increase a throughput considerably. A switching instruction which selects either a normal connection or cross connection is generated on the basis of an initial value previously set by a connection switching judging block (3) and a value stored in a register of a block ((A) 1). In parallel to this operation, divided results and a value output from the preceding stage are stored in respective blocks ((B) 2) and one of a normal connection calculation and a cross connection calculation is carried out in response to the switching instruction. Further, a value output from the final stage of the blocks ((B) 2) is stored in the block ((A) 1), and one of the normal connection calculation and the cross connection calculation is performed in response to the switching instruction. Then, the calculated result is supplied to the respective blocks ((B) 2) to effect an Euclidean mutual division calculation.
Inventors
- 👤 Masayuki Hattori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:26
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151; G; G06; G06F; G06F7/00; G06F7/60; G06F7/72; G06F7/724; G06F7/726
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
221 words
A mutual division circuit comprising: first calculating means including a plurality of cascaded registers the number of which corresponds to that of corrections and which store therein coefficient data of respective polynomials Ri(X), Qi(X), λi(X) and μi(X), said first calculating means storing therein divided results and a value output from a preceding stage and for effecting one of a normal connection calculation and a cross connection calculation in response to a switching instruction; second calculating means forming said preceding stage including a plurality of registers for storing therein the coefficient data of said polynomials Ri(X), Qi(X), λi(X) and μi(X) and dividers for dividing outputs of said registers which store therein the coefficient data of said polynomials Ri(X), Qi(X), λi(X) and μi(X), said second calculating means storing therein a value output from the final stage of said first calculating means and carrying out one of a normal connection division calculation and a cross connection division calculation in response to a switching instruction to thereby supply the calculated result to said first calculating means; and switching judging means for generating said switching instruction for designating one of the normal connection and the cross connection on the basis of a predetermined initial value and a value stored in said second calculating means and supplying the switching instruction to said first and second calculating means.
Claim 2
Dependent Claim
221 words
A mutual division circuit comprising: first calculating means including a plurality of cascaded registers the number of which corresponds to that of corrections and which store therein coefficient data of respective polynomials Ri(X), Qi(X), λi(X) and μi(X), said first calculating means storing therein divided results and a value output from a preceding stage and for effecting one of a normal connection calculation and a cross connection calculation in response to a switching instruction; second calculating means forming said preceding stage including a plurality of registers for storing therein the coefficient data of said polynomials Ri(X), Qi(X), λi(X) and μi(X) and dividers for dividing outputs of said registers which store therein the coefficient data of said polynomials Ri(X), Qi(X), λi(X) and μi(X), said second calculating means storing therein a value output from the final stage of said first calculating means and carrying out one of a normal connection division calculation and a cross connection division calculation in response to a switching instruction to thereby supply the calculated result to said first calculating means; and switching judging means for generating said switching instruction for designating one of the normal connection and the cross connection on the basis of a predetermined initial value and a value stored in said second calculating means and supplying the switching instruction to said first and second calculating means.
Claim 3
Dependent Claim
22 words
The mutual division circuit according to claim 1, wherein said 2t-1 first calculating means are cascaded if said correction number is t.
Claim 4
Dependent Claim
110 words
The mutual division circuit according to claim 1, wherein said first calculating means comprises multipliers for multiplying outputs of said registers which store therein coefficient data of said polynomial Ri(X) (or Qi(X)) and divided results of said dividers, adders for adding the outputs of said registers which store therein coefficient data of said polynomial Qi(X) (or Ri(X)) and outputs of said multipliers, multipliers for multiplying outputs of said registers which store therein coefficient data of said polynomial λi(X) (or μi(X)) and divided outputs of said dividers and adders for adding outputs of said registers which store therein coefficient data of said polynomial μi(X) (or λi(X)) and outputs of said multipliers.
Claim 5
Dependent Claim
62 words
The mutual division circuit according to claim 1, wherein said second calculating means comprises multipliers for multiplying outputs of said registers which store therein coefficient data of said polynomial λi(X) (or μi(X)) and divided outputs of said dividers and adders for adding outputs of said registers which store therein coefficient data of said polynomial μi(X) (or λi(X)) and outputs of said multipliers.
Claim 6
Dependent Claim
111 words
The mutual division circuit according to claim 1, wherein said switching judging means comprises two registers for respectively storing order data dRi and dQi, comparing means for comparing outputs of said two registers, detecting means for detecting whether or not the output of said register which stores therein coefficient data of said polynomial Ri(X) of said second calculating means is 0; and judging means for generating said switching instruction for designating the cross-connection to said first and second calculating means if dR1<DQi and coefficient data of said polynomial Ri(X) is not zero on the basis of a compared result of said comparing means and a detected result of said detecting means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |