Circuit for operating finite fields

Claim 2

A circuit for operating a multiplication or a division in relation to the arbitrary elements α i and α over a finite field, where α is a root of a primitive polynomial of said finite field, comprising: an accumulator for storing said arbitrary element α i ; a register for storing a vector representation of said primative polynomial, corresponding to the root α; an adder for performing a (mod. 2) addition using as operands the contents of said accumulator and signals from said register; and a control section for controlling the bit-shift in said accumulator and the operation of said adder in accordance with a program.

Claim 5

A circuit for operating a multiplication or a division in relation to arbitrary elements α i (where i is an integer) and α over a finite field of 2 m (where m is a positive integer), where α is a root of a primative polynomial of the finite field, comprising: first memory means for storing first digital data of at least m+1 bits corresponding to a vector representation of the primitive polynomial; second memory means for storing second digital data of m bits corresponding to a vector representation of the arbitrary element α i ; accumulator means having a capacity of at least m+1 bits and connected to said second memory mean; third memory means connected between the most significant bit end and the least significant bit end of said accumulator means and for storing third digital data of 1 bits corresponding to a digital value of "0"; said adder means connected to said first memory means and accumulator means and for modulo-2-adding the contents of said accumulator means and the first digital data from said first memory means as operands; program memory means for storing a program; control means for controlling the loading of the second digital data from said second memory means into said accumulator means and for shifting the contents of said accumulator means by one bit to the most significant bit side in a case of multiplication or to the least significant bit side in a case of division; discriminating means for discriminating the m-th significant bit in the case of multiplication or the least significant bit in the case of division of the contents of said accumulator means and for producing a control signal to be provided to said program memory means; and said control means further controlling the addition of the contents of said accumulator means and the first digital data from said first memory means in said adder means so as to produce sum data, according to the control signal from said discriminating means, and for storing said sum data or the contents of said accumulator means into said second memory means.

Claim 6

A circuit for operating a multiplication or a division in relation to arbitrary elements α i (where i is an integer) and α over a finite field of 2 m (where m is a positive integer), where α is a root of a primative polynomial of the finite field, comprising: first memory means for storing first digital data of at least m+1 bits corresponding to a vector representation of the primitive polynomial; second memory means for storing second digital data of m bits corresponding to a vector representation of the arbitrary element α i ; accumulator means having a capacity of at least m+1 bits and connected to said second memory mean; third memory means connected between the most significant bit end and the least significant bit end of said accumulator means and for storing third digital data of 1 bits corresponding to a digital value of "0"; said adder means connected to said first memory means and accumulator means and for modulo-2-adding the contents of said accumulator means and the first digital data from said first memory means as operands; program memory means for storing a program; control means for controlling the loading of the second digital data from said second memory means into said accumulator means and for shifting the contents of said accumulator means by one bit to the most significant bit side in a case of multiplication or to the least significant bit side in a case of division; discriminating means for discriminating the m-th significant bit in the case of multiplication or the least significant bit in the case of division of the contents of said accumulator means and for producing a control signal to be provided to said program memory means; and said control means further controlling the addition of the contents of said accumulator means and the first digital data from said first memory means in said adder means so as to produce sum data, according to the control signal from said discriminating means, and for storing said sum data or the contents of said accumulator means into said second memory means.