Processing circuits for operating on digital data words which are elements of a Galois field

Claim 2

A processing circuit for operating on digital data words which form elements α i of a Galois field GF(2 m ) having an irreducible root α, the elements each corresponding to a power α i of the irreducible root α, the circuit comprising: an input bus (5) for supplying said digital data words as input elements; converting circuit means (1) to which said input elements α i are applied and generating in response corresponding exponents for said input elements α i ; additive combining means (2) for combining the exponents of a plurality of said input elements & to form a resulting sum thereof; and reverse converting circuit means (3) to which said sum is applied for generating in response thereto an output data element that corresponds to said irreducible root α taken to the power of said resulting sum.

Claim 3

A circuit according to claim 1 wherein said converting circuit means includes a randomly accessible memory device (1) to which said input elements α i are supplied as address codes and which provides said exponents as stored data.

Claim 4

A circuit according to claim 2 wherein said memory device is a read- only memory (1).

Claim 5

A circuit according to claim 1 wherein said reverse converting circuit means includes a randomly accessible memory device (3) to which said resulting sum is supplied as an address code and which provides said input elements α i as stored data.

Claim 6

A circuit according to claim 4 wherein said memory device is a read- only memory (3).

Claim 7

A circuit according to claim 1 wherein said Galois field extends over 2 m (m being a whole number) and said combining means includes a modulo-(2 m- 1) adder (2).

Claim 8

A circuit according to claim 6 wherein said combining means includes an inverter (4A, 4B) connected between one such converting circuit means (1B, 1A) and said adder (2) so that said resulting sum forms a difference between exponents of corresponding input elements α i , and said reverse converting circuit means (3) provides the quotient of said input words.

Claim 9

A circuit according to claim 6 wherein said combining means includes an inverter (4C) disposed between said adder (2) and said reverse converting circuit means (3) so that said reverse converting circuit means (4) provides an output which is the inverse of the product of said input elements α i .

Claim 10

A circuit according to claim 6 or claim 7 wherein said inverter (4A, 4B, 4C) operates by forming a complement of the digital signal applied thereto.

Claim 11

A circuit according to claim 1 further comprising means (10) providing a detecting signal if one of said input elements α 1 is a zero element, and means (14) for converting the output data element to a predetermined value in response to said detecting signal, such that any quotient resulting from division by zero is compensated.

Claim 12

A processing circuit for operating on digital data words of a predetermined bit length m such that the digital data words form elements α i of a Galois field (2 m ) having an irreducible root α, each said element corresponding to a power α i of the irreducible root α, the circuit comprising: an input data bus (5) for supplying said digital data words in time sequence; a conversion device (1) to which said digital data words are applied in sequence as said elements and in response thereto providing corresponding exponents i thereof; a first register (6) coupled to said conversion circuit (1) for storing said exponents i; a controlled inversion circuit (4) following said first register (6) and controlled by an inversion control signal so that said controlled inversion circuit (4) provides, as an output thereof, said exponents i without inversion when said inversion control signal has one sense and with inversion when said inversion control signal has another, complementary sense; a modulo-(2m-1) adder (2) having first and second inputs and an output, with the output of said controlled inversion circuit (4) being coupled to said first input thereof; a second register (7) having an input coupled to the output of said adder (2) for storing the contents thereof and having an output; a controlled gate circuit (11) having an input coupled to the output of said second register (7) and an output coupled to thesecond input of said adder (2) and controlled by a gate control signal selectively to pass the contents of said second register (7) to said adder (2); and a reverse conversion device (3) coupled to the output of said second register (7) to receive the contents thereof, and in response thereto to provided an output data word that is the power of said irreducible element corresponding to the contents of said second register (7).

Claim 13

A processing circuit for operating on digital data words of a predetermined bit length m such that the digital data words form elements α i of a Galois field (2 m ) having an irreducible root α, each said element corresponding to a power α i of the irreducible root α, the circuit comprising: an input data bus (5) for supplying said digital data words in time sequence; a conversion device (1) to which said digital data words are applied in sequence as said elements and in response thereto providing corresponding exponents i thereof; a first register (6) coupled to said conversion circuit (1) for storing said exponents i; a controlled inversion circuit (4) following said first register (6) and controlled by an inversion control signal so that said controlled inversion circuit (4) provides, as an output thereof, said exponents i without inversion when said inversion control signal has one sense and with inversion when said inversion control signal has another, complementary sense; a modulo-(2m-1) adder (2) having first and second inputs and an output, with the output of said controlled inversion circuit (4) being coupled to said first input thereof; a second register (7) having an input coupled to the output of said adder (2) for storing the contents thereof and having an output; a controlled gate circuit (11) having an input coupled to the output of said second register (7) and an output coupled to thesecond input of said adder (2) and controlled by a gate control signal selectively to pass the contents of said second register (7) to said adder (2); and a reverse conversion device (3) coupled to the output of said second register (7) to receive the contents thereof, and in response thereto to provided an output data word that is the power of said irreducible element corresponding to the contents of said second register (7).

Claim 14

A circuit according to claim 11 further comprising a zero element detector (10) coupled to said data bus (5) and supplying to said first register (6) a detecting signal of one sense to indicate that an associated one of the input data words is zero but of another, complementary sense otherwise; logic gate means (12, 13) supplying the detecting signal stored in said first register (6) to said second register (7); and an output gate (14) having a control input controlled by the detecting signal stored in said second register (7) and a data input coupled to said reverse conversion device (3) for passing the output of said reverse conversion device (3) when said detecting signal stored in said second register (7) has said other sense and blocking said output when said detecting signal has said one sense.

Claim 15

A circuit according to claim 12 wherein said logic gate means includes an AND gate (13) having inputs to receive the detecting signal stored in said second register (7) and said gate control signal, respectively, and an output; and an OR gate (12) having inputs coupled to the output of said AND gate (13) and to said first register (6) to receive the detecting signal stored therein, respectively, and an output coupled to said second register (7).

Claim 16

A circuit according to claim 11 wherein said bit length m is eight bits and said adder 2 is a modulo-255 adder.