Patent US5367284A successfully refreshed from Google Patents.
US5367284A
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Thin film resistor and method for manufacturing the same
Assignee: Texas Instruments Inc
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Filing: 1993-05-10
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Granted: 1994-11-22
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Expires: 2013-05-10
Abstract
Abstract An inverted thin film resistor structure comprises a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads (e.g. Al 36) overlaying a supporting layer (e.g. SiO2 32), an interlevel dielectric layer (e.g. SiO2 40) overlaying the supporting layer, and planarized so as to expose a top contact portion of the metallic interconnect leads, and an inverted thin film resistor (e.g. TaN 44) overlaying a portion of the planarized interlevel dielectric layer and overlaying the exposed top contact portion of the metallic interconnect leads. The novel inverted thin film resistor structure does not require a protective metal layer and does not require any vias in direct contact with the resistor. In addition, both the thin film resistor and the metallic interconnect can be formed with pattern and etch techniques. Improved resistor control and reliability are generally achieved since the resistor film is deposited on a substantially planar surface, and resistor length is determined by the spacing of the metallic leads rather than the size of the vias.
Inventors
- 👤 Frank J. Morris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:07
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D1/474; H01; H01C; H01C1/00; H01C1/14
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
135 words
A method of fabricating a microelectronic inverted thin film resistor structure, said method comprising: (a) forming a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads, on a supporting layer; (b) forming an interlevel dielectric layer on said metallic interconnect layer and said supporting layer; (c) planarizing said interlevel dielectric layer so as to expose a top contact portion of said metallic interconnect leads between 1 and 1000 angstroms above said interlevel dielectric layer; and (d) forming an inverted thin film resistor on said planarized interlevel dielectric layer and on said exposed top contact portion of said metallic interconnect leads, whereby said inverted thin film resistor structure does not require a protective metal layer on said resistor and does not require said resistor to be an etch stop for subsequent processing.
Claim 2
Independent Claim
135 words
A method of fabricating a microelectronic inverted thin film resistor structure, said method comprising: (a) forming a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads, on a supporting layer; (b) forming an interlevel dielectric layer on said metallic interconnect layer and said supporting layer; (c) planarizing said interlevel dielectric layer so as to expose a top contact portion of said metallic interconnect leads between 1 and 1000 angstroms above said interlevel dielectric layer; and (d) forming an inverted thin film resistor on said planarized interlevel dielectric layer and on said exposed top contact portion of said metallic interconnect leads, whereby said inverted thin film resistor structure does not require a protective metal layer on said resistor and does not require said resistor to be an etch stop for subsequent processing.
Claim 3
Dependent Claim
26 words
The method according to claim 1, said method further comprising forming an upper level dielectric layer on and substantially covering said inverted thin film resistor structure.
Claim 4
Dependent Claim
36 words
The method according to claim 1, wherein said inverted thin film resistor formation comprises the steps of: (a) depositing a resistive layer; and (b) photolithographically defining and etching a predetermined resistor pattern in said resistive layer.
Claim 5
Dependent Claim
25 words
The method according to claim 1, wherein said resistor has a length defined by a predetermined spacing between said top contact portion of said leads.
Claim 6
Dependent Claim
16 words
The method according to claim 1, wherein said supporting layer is a lower level dielectric layer.
Claim 7
Dependent Claim
14 words
The method according to claim 1, wherein said supporting layer is a semiconductor substrate.
Claim 8
Dependent Claim
28 words
The method according to claim 1, wherein said metallic interconnect layer is selected from the group consisting of: Al, Au, Cu, Ti, W, AlCu, TiW/Au, and combinations thereof.
Claim 9
Dependent Claim
26 words
The method according to claim 1, wherein said inverted thin film resistor is selected from the group consisting of: TaN, Cermet, TiN, TiW, and combinations thereof.
Claim 10
Dependent Claim
29 words
The method according to claim 1, wherein said interlevel dielectric layer is selected from the group consisting of: SiO 2 , Si 3 N 4 , and combinations thereof.
Claim 11
Dependent Claim
30 words
The method according to claim 1, wherein said interlevel dielectric planarizing exposes said top contact portion of said interconnect leads between 300 and 700 angstroms above said interlevel dielectric layer.
Claim 12
Dependent Claim
30 words
The method according to claim 1, wherein said interlevel dielectric planarizing exposes said top contact portion of said interconnect leads between 450 and 550 angstroms above said interlevel dielectric layer.
Claim 13
Dependent Claim
16 words
The method according to claim 1, wherein said resistor is formed by photolithographic defining and etching.
Claim 14
Dependent Claim
107 words
A microelectronic inverted thin film resistor structure comprising: a substantially planar interlevel dielectric layer overlaying a supporting layer; a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads overlaying said supporting layer, wherein an exposed portion of said leads extends between 1 and 1000 angstroms above said dielectric layer; and an inverted thin film resistor overlaying a portion of said planar interlevel dielectric layer and overlaying said exposed portion of said metallic interconnect leads, wherein said inverted thin film resistor structure does not contain a protective metal layer on said resistor and does not contain any vias in direct contact with said resistor.
Claim 15
Dependent Claim
107 words
A microelectronic inverted thin film resistor structure comprising: a substantially planar interlevel dielectric layer overlaying a supporting layer; a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads overlaying said supporting layer, wherein an exposed portion of said leads extends between 1 and 1000 angstroms above said dielectric layer; and an inverted thin film resistor overlaying a portion of said planar interlevel dielectric layer and overlaying said exposed portion of said metallic interconnect leads, wherein said inverted thin film resistor structure does not contain a protective metal layer on said resistor and does not contain any vias in direct contact with said resistor.
Claim 16
Dependent Claim
24 words
The structure of claim 13, said structure further comprising an upper level dielectric layer on and substantially covering said inverted thin film resistor structure.
Claim 17
Dependent Claim
15 words
The structure of claim 13, wherein said supporting layer is a lower level dielectric layer.
Claim 18
Dependent Claim
13 words
The structure of claim 13, wherein said supporting layer is a semiconductor substrate.
Claim 19
Dependent Claim
27 words
The structure of claim 13, wherein said metallic interconnect layer is selected from the group consisting of: Al, Au, Cu, Ti, W, AlCu, TiW/Au, and combinations thereof.
Claim 20
Dependent Claim
25 words
The structure of claim 13, wherein said inverted thin film resistor is selected from the group consisting of: TaN, Cermet, TiN, TiW, and combinations thereof.
Claim 21
Dependent Claim
28 words
The structure of claim 13, wherein said interlevel dielectric layer is selected from the group consisting of: SiO 2 , Si 3 N 4 , and combinations thereof.
Claim 22
Dependent Claim
24 words
The structure of claim 13, wherein said exposed portion of said interconnect leads extends between 300 and 700 angstroms above said interlevel dielectric layer.
Claim 23
Dependent Claim
24 words
The structure of claim 13, wherein said exposed portion of said interconnect leads extends between 450 and 550 angstroms above said interlevel dielectric layer.
Claim 24
Dependent Claim
23 words
The structure of claim 13, wherein said resistor has a length defined by a predetermined spacing between said exposed portion of said leads.
Claim 25
Independent Claim
140 words
A method of fabricating microelectronic inverted thin film resistor structures, said method comprising: (a) forming a first inverted thin film resistor structure comprising the steps of: (i) forming a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads, on a supporting layer; (ii) forming an interlevel dielectric layer on said metallic interconnect layer and said supporting layer; (iii) planarizing said interlevel dielectric layer so as to expose a top contact portion of said metallic interconnect leads; and (iv) forming an inverted thin film resistor on said planarized interlevel dielectric layer and on said exposed top contact portion of said metallic interconnect leads; (b) forming an upper level dielectric layer on and substantially covering said first inverted thin film resistor structure; and (c) forming a second inverted thin film resistor structure on said upper level dielectric layer.
Claim 26
Independent Claim
140 words
A method of fabricating microelectronic inverted thin film resistor structures, said method comprising: (a) forming a first inverted thin film resistor structure comprising the steps of: (i) forming a metallic interconnect layer having predetermined patterns delineating two or more metallic interconnect leads, on a supporting layer; (ii) forming an interlevel dielectric layer on said metallic interconnect layer and said supporting layer; (iii) planarizing said interlevel dielectric layer so as to expose a top contact portion of said metallic interconnect leads; and (iv) forming an inverted thin film resistor on said planarized interlevel dielectric layer and on said exposed top contact portion of said metallic interconnect leads; (b) forming an upper level dielectric layer on and substantially covering said first inverted thin film resistor structure; and (c) forming a second inverted thin film resistor structure on said upper level dielectric layer.
Claim 27
Dependent Claim
20 words
The method according to claim 23, wherein said first and second inverted thin film resistor structures comprise different sheet resistances.
Claim 28
Dependent Claim
36 words
The method according to claim 23, wherein said inverted thin film resistor formation comprises the steps of: (a) depositing a resistive layer; and (b) photolithographically defining and etching a predetermined resistor pattern in said resistive layer.
Claim 29
Dependent Claim
30 words
The method according to claim 23, wherein said interlevel dielectric planarizing exposes said top contact portion of said interconnect leads between 300 and 700 angstroms above said interlevel dielectric layer.
Claim 30
Dependent Claim
30 words
The method according to claim 23, wherein said interlevel dielectric planarizing exposes said top contact portion of said interconnect leads between 450 and 550 angstroms above said interlevel dielectric layer.
References Cited (Backward Citations)
US4676867A
Cited
US4968964A
Cited
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