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US5366919A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a memory cell of a semiconductor memory device

Assignee: United Microelectronics Corp
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Filing: 1993-10-13
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Granted: 1994-11-22
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Expires: 2013-10-13
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Abstract

Abstract A method of making a memory cell having a transistor and a capacitor of a semiconductor memory device comprises the steps of: forming on a substrate on a surface of which the transistor is formed, an interlayer insulating film having a contact hole reaching a selected portion of the transistors; introducing a selected metal into a surface of the selected portion of the transistor exposed to the contact hole and a surface of the interlayer insulating film at portions thereof where a lower electrode of the capacitor is to be formed; forming a first conductive film having a pattern of the lower electrode of the capacitor by depositing a selected conductive material on the portions where the selected metal has been introduced; forming a capacitor insulating film on the first conductive film; and forming a second conductive film which provides an upper electrode of the capacitor on the capacitor insulating film; wherein the selected conductive material and the selected metal have such a relationship with each other that, when the first conductive layer is formed by depositing the selected conductive material on the portions where the selected metal has been introduced, the selected metal acts as a catalyzer to cause the selected conductive material to develop whisker crystal growth, thereby forming fine projections on an upper surface of the first conductive film.

Inventors

  • 👤 Kimiaki Tanaka
  • 👤 Hideki Takeuchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 03:24
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10B; H10B12/00; H10B12/30; H10B12/31; Y; Y10; Y10S; Y10S438/00; Y10S438/903

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 213 words
A method of making a memory cell having a transistor and a capacitor of a semiconductor memory device, comprising the steps of: forming, on a substrate in a surface of which the transistor is formed, an interlayer insulating film having a contact hole reaching a source/drain region of said transistor; introducing a metal into a surface of said source/drain region of said transistor exposed to said contact hole and a surface portion of said interlayer insulating film at portions thereof where a lower electrode of said capacitor is to be formed; forming a first conductive film having a pattern of the lower electrode of said capacitor by depositing a conductive material on the portions where said metal has been introduced; forming a capacitor insulating film on said conductive film; and forming a second conductive film which provides an upper electrode of said capacitor on said capacitor insulating film; wherein said conductive material and said metal have such a relationship with each other that, when said first conductive film is formed by depositing the conductive material on the portions where the metal has been introduced, said metal acts as a catalyzer to cause said conductive material to develop whisker crystal growth, thereby forming fine projections on an upper surface of said first conductive film.
Claim 2
Independent Claim 213 words
A method of making a memory cell having a transistor and a capacitor of a semiconductor memory device, comprising the steps of: forming, on a substrate in a surface of which the transistor is formed, an interlayer insulating film having a contact hole reaching a source/drain region of said transistor; introducing a metal into a surface of said source/drain region of said transistor exposed to said contact hole and a surface portion of said interlayer insulating film at portions thereof where a lower electrode of said capacitor is to be formed; forming a first conductive film having a pattern of the lower electrode of said capacitor by depositing a conductive material on the portions where said metal has been introduced; forming a capacitor insulating film on said conductive film; and forming a second conductive film which provides an upper electrode of said capacitor on said capacitor insulating film; wherein said conductive material and said metal have such a relationship with each other that, when said first conductive film is formed by depositing the conductive material on the portions where the metal has been introduced, said metal acts as a catalyzer to cause said conductive material to develop whisker crystal growth, thereby forming fine projections on an upper surface of said first conductive film.
Claim 3
Dependent Claim 16 words
A method according to claim 1, wherein said first conductive film is a polycrystalline silicon film.
Claim 4
Dependent Claim 30 words
A method according to claim 1, wherein said metal includes at least one selected from the group consisting of tungsten, iron, chrome, nickel, gold, silver, copper, molybdenum, aluminum and platinum.
Claim 5
Dependent Claim 16 words
A method according to claim 3, wherein said first conductive film is a polycrystalline silicon film.

References Cited (Backward Citations)

US5102832A Cited
US5134086A Cited
US5302540A Cited
US5244842A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-11-21 1998-05-23 1998-11-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-11-21 2002-05-23 2002-11-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-11-21 2006-05-23 2006-11-22 $7700.00 Window Closed / Lapsed

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