Method of making a buried bit line DRAM cell

Claim 1

A method of manufacture of a semiconductor device, comprising the following steps: a) implanting ions of dopant into a doped semiconductor substrate of said device, said dopant being of sufficient concentration to form a buried conductor region therein, b) forming a dielectric layer on the surface of said doped substrate whereby a thicker dielectric is formed over said implanted ions, c) forming a first polysilicon layer on said silicon dioxide layer, d) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask to form conductor lines, e) forming a second dielectric layer on the surface of said first polysilicon layer on said device, f) forming a second polysilicon layer on said second dielectric layer, g) forming a photolithographic mask and etching portions of said second polysilicon layer to form a first capacitor plate therefrom, h) forming a third dielectric layer on the surface of said second polysilicon layer on said device, i) forming a third polysilicon layer on said third dielectric layer, and j) patterning said third polysilicon layer by forming a mask and etching said polysilicon through said mask to form a top capacitor plate.

Claim 2

A method of manufacture of a semiconductor device, comprising the following steps: a) implanting ions of dopant into a doped semiconductor substrate of said device, said dopant being of sufficient concentration to form a buried conductor region therein, b) forming a dielectric layer on the surface of said doped substrate whereby a thicker dielectric is formed over said implanted ions, c) forming a first polysilicon layer on said silicon dioxide layer, d) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask to form conductor lines, e) forming a second dielectric layer on the surface of said first polysilicon layer on said device, f) forming a second polysilicon layer on said second dielectric layer, g) forming a photolithographic mask and etching portions of said second polysilicon layer to form a first capacitor plate therefrom, h) forming a third dielectric layer on the surface of said second polysilicon layer on said device, i) forming a third polysilicon layer on said third dielectric layer, and j) patterning said third polysilicon layer by forming a mask and etching said polysilicon through said mask to form a top capacitor plate.

Claim 7

A method of manufacture of a semiconductor device, comprising the following steps: a) implanting ions into a doped substrate in a semiconductor substrate of said device to form at least one conductive region therein, said dopant being of sufficient concentration to form a buried conductor region therein, b) forming a silicon dioxide layer on the surface of said doped substrate whereby a thicker oxide is formed over said implanted ions, c) forming a first polysilicon layer on said silicon dioxide layer, d) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask, e) forming a first inter polysilicon layer on the surface of said first polysilicon layer on said device, f) forming a mask on said first inter polysilicon layer and etching of the exposed portions of said inter polysilicon layer exposing the surface of said doped substrate, g) forming a second polysilicon layer on said inter polysilicon layer, h) forming a photolithographic mask on said second polysilicon layer with openings therein, i) patterning said second polysilicon layer by etching said second polysilicon layer through said openings in said mask to form a first capacitor plate therefrom, j) forming a second inter polysilicon layer on the surface of said second polysilicon layer on said device, k) forming a third polysilicon layer on said second inter polysilicon layer, l) forming a photolithographic mask on said third polysilicon layer with openings therein, m) patterning said third polysilicon layer by etching said third polysilicon layer through said mask to form a top capacitor plate, n) forming a second silicon dioxide layer on the exposed surface of said doped substrate, and o) depositing a layer of BPSG upon said third layer of polysilicon, whereby preliminary manufacture of said device is completed.

Claim 8

A method of manufacture of a semiconductor device, comprising the following steps: a) implanting ions into a doped substrate in a semiconductor substrate of said device to form at least one conductive region therein, said dopant being of sufficient concentration to form a buried conductor region therein, b) forming a silicon dioxide layer on the surface of said doped substrate whereby a thicker oxide is formed over said implanted ions, c) forming a first polysilicon layer on said silicon dioxide layer, d) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask, e) forming a first inter polysilicon layer on the surface of said first polysilicon layer on said device, f) forming a mask on said first inter polysilicon layer and etching of the exposed portions of said inter polysilicon layer exposing the surface of said doped substrate, g) forming a second polysilicon layer on said inter polysilicon layer, h) forming a photolithographic mask on said second polysilicon layer with openings therein, i) patterning said second polysilicon layer by etching said second polysilicon layer through said openings in said mask to form a first capacitor plate therefrom, j) forming a second inter polysilicon layer on the surface of said second polysilicon layer on said device, k) forming a third polysilicon layer on said second inter polysilicon layer, l) forming a photolithographic mask on said third polysilicon layer with openings therein, m) patterning said third polysilicon layer by etching said third polysilicon layer through said mask to form a top capacitor plate, n) forming a second silicon dioxide layer on the exposed surface of said doped substrate, and o) depositing a layer of BPSG upon said third layer of polysilicon, whereby preliminary manufacture of said device is completed.