Method of manufacturing a contact of a highly integrated semiconductor device

Claim 1

A method of manufacturing a contact of a highly integrated semiconductor device, comprising the steps of: forming a MOS transistor having gate, source, and drain electrodes and a field oxide on a silicon substrate; forming a first insulating layer that completely covers said MOS transistor and field oxide; forming a polyimide pattern only on contact areas located on top of the source electrode and drain electrode after coating a photo-sensitive polyimide over the first insulating layer; forming a second insulating layer over the device, particularly on said polyimide pattern and then forming a second insulating layer pattern by carrying out an etch back process until a surface of said polyimide pattern is exposed; removing the exposed polyimide pattern using a plasma etching process; forming a spacer on side walls of the gate electrode by carrying out a blanket etching process on the first insulating layer that has been exposed by said plasma etching process while simultaneously forming contact areas where the source electrode and the drain electrode are exposed; depositing a polysilicon layer over the second insulating layer pattern and forming several polysilicon pads that are in contact with the drain electrode or the source electrode by carrying out an etch back process until a surface of the second insulating layer pattern is exposed; depositing a third insulating layer over the device, including said polysilicon pads; and exposing each of said several polysilicon pads by removing a portion of the third insulating layer and depositing a conducting layer in contact with the exposed polysilicon pad.

Claim 2

A method of manufacturing a contact of a highly integrated semiconductor device, comprising the steps of: forming a MOS transistor having gate, source, and drain electrodes and a field oxide on a silicon substrate; forming a first insulating layer that completely covers said MOS transistor and field oxide; forming a polyimide pattern only on contact areas located on top of the source electrode and drain electrode after coating a photo-sensitive polyimide over the first insulating layer; forming a second insulating layer over the device, particularly on said polyimide pattern and then forming a second insulating layer pattern by carrying out an etch back process until a surface of said polyimide pattern is exposed; removing the exposed polyimide pattern using a plasma etching process; forming a spacer on side walls of the gate electrode by carrying out a blanket etching process on the first insulating layer that has been exposed by said plasma etching process while simultaneously forming contact areas where the source electrode and the drain electrode are exposed; depositing a polysilicon layer over the second insulating layer pattern and forming several polysilicon pads that are in contact with the drain electrode or the source electrode by carrying out an etch back process until a surface of the second insulating layer pattern is exposed; depositing a third insulating layer over the device, including said polysilicon pads; and exposing each of said several polysilicon pads by removing a portion of the third insulating layer and depositing a conducting layer in contact with the exposed polysilicon pad.

Claim 18

A method of manufacturing a contact of a highly integrated semiconductor device, comprising the steps of: forming a MOS transistor having gate, source and drain electrodes, and a field oxide on a silicon substrate; forming a first insulating layer that completely covers said MOS transistor and field oxide; forming a second insulating layer over the first insulating layer and etching the second insulating layer until a surface of the first insulating layer is exposed by carrying out an etch back process in which the etch selectivity to the second insulating layer is higher than that of the first insulating layer; depositing a third insulating layer over the device and, using a mask patterning process, removing portions of the third insulating layer located on contact areas for a bit line and a charge storage node; forming a first insulating layer spacer on side walls of the third insulating layer adjacent the contact areas; forming a contact hole by removing the second insulating layer that has been exposed and the first insulating layer located below the exposed second insulating layer; and depositing a doped polysilicon layer over the device to fill said contact hole and etching back the doped polysilicon layer to form a polysilicon contact pad on the contact hole.

Claim 19

A method of manufacturing a contact of a highly integrated semiconductor device, comprising the steps of: forming a MOS transistor having gate, source and drain electrodes, and a field oxide on a silicon substrate; forming a first insulating layer that completely covers said MOS transistor and field oxide; forming a second insulating layer over the first insulating layer and etching the second insulating layer until a surface of the first insulating layer is exposed by carrying out an etch back process in which the etch selectivity to the second insulating layer is higher than that of the first insulating layer; depositing a third insulating layer over the device and, using a mask patterning process, removing portions of the third insulating layer located on contact areas for a bit line and a charge storage node; forming a first insulating layer spacer on side walls of the third insulating layer adjacent the contact areas; forming a contact hole by removing the second insulating layer that has been exposed and the first insulating layer located below the exposed second insulating layer; and depositing a doped polysilicon layer over the device to fill said contact hole and etching back the doped polysilicon layer to form a polysilicon contact pad on the contact hole.