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US5363326A
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US
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Semiconductor memory device having crossed word lines, and method of operating same
Assignee: Sony Corp
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Filing: 1993-01-13
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Granted: 1994-11-08
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Expires: 2013-01-13
Abstract
Abstract A main portion of a first word line extends in a direction connecting one diffusion region to the other diffusion region of an access transistor and is located between memory cells, and diverging portions of the first word line alternately extend from both sides of the main portion of the first word line to corresponding adjacent memory cells. A bit line extends in a direction perpendicular to the direction connecting one diffusion region to the other diffusion region, and a second word line extends along the diverging portion of the first word line. When stored data is to be read out from a memory cell, a positive voltage is applied to one first word line corresponding to the memory cell whose data is to be read out, and a zero voltage is applied to the remaining first word lines. Furthermore, a zero voltage is applied to one second word line corresponding to the memory cell whose data is to be read out, and a negative voltage which cancels the positive voltage applied to the first word line is applied to the remaining second word lines.
Inventors
- 👤 Hideharu Nakajima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:02
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
A semiconductor device comprising: a plurality of memory cells arranged in an array of rows and columns, each memory cell having an access transistor and a storage capacitor which is connected to one diffusion region of the access transistor; a bit line connected to the other diffusion region of the access transistor and extending in a second direction perpendicular to a first direction defined as the direction connecting said one diffusion region and the other diffusion region of said access transistor; a first word line having a main portion extending in said first direction, located between adjacent memory cells, and having diverging portions alternately extending from both sides of said main portion of the first word line to corresponding adjacent memory cells; and a second word line extending in said second direction and located along said diverging portion of the first word line.
Claim 2
Dependent Claim
143 words
A semiconductor device comprising: a plurality of memory cells arranged in an array of rows and columns, each memory cell having an access transistor and a storage capacitor which is connected to one diffusion region of the access transistor; a bit line connected to the other diffusion region of the access transistor and extending in a second direction perpendicular to a first direction defined as the direction connecting said one diffusion region and the other diffusion region of said access transistor; a first word line having a main portion extending in said first direction, located between adjacent memory cells, and having diverging portions alternately extending from both sides of said main portion of the first word line to corresponding adjacent memory cells; and a second word line extending in said second direction and located along said diverging portion of the first word line.
Claim 3
Dependent Claim
31 words
A semiconductor memory device according to claim 1, wherein said second word line is formed on an insulation layer which is formed on said diverging portion of the first word line.
Claim 4
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein said second word line is formed on an insulation layer which is formed on said diverging portion of the first word line and on an insulation layer which is formed on the surface of said one diffusion region of the access transistor.
Claim 5
Dependent Claim
46 words
A semiconductor memory device according to claim 1, wherein said second word line is formed on an insulation layer which is formed on the surface of said one diffusion region of the access transistor and is adjacent to said diverging portion of the first word line.
Claim 6
Dependent Claim
57 words
A semiconductor memory device according to claim 1, wherein the connection between said storage capacitor and said one diffusion region of the access transistor is formed in the region which is surrounded by said main portion of the first word line, said diverging portion of the first word line, said second word line and said bit line.
Claim 7
Independent Claim
178 words
A method of operating a semiconductor device containing a plurality of memory cells each having an access transistor and a storage capacitor which is connected to one diffusion region of the access transistor, a plurality of bit lines connected to the other diffusion region of the access transistor, a plurality of first word lines each having a main portion and diverging portions, and a plurality of second word lines located along diverging portions of the first word line, comprising: applying a positive voltage to a first word line corresponding to the memory cell whose stored signal is read out; applying a zero voltage to other first word lines; applying a zero voltage to second word lines corresponding to said memory cell whose stored signal is read out; applying a negative voltage to other second word lines, thereby canceling the positive voltage applied to the first word line corresponding to the memory cell whose stored signal is read out; and outputting the stored signal from the bit lines corresponding to the memory cell whose stored signal is read out.
Claim 8
Independent Claim
178 words
A method of operating a semiconductor device containing a plurality of memory cells each having an access transistor and a storage capacitor which is connected to one diffusion region of the access transistor, a plurality of bit lines connected to the other diffusion region of the access transistor, a plurality of first word lines each having a main portion and diverging portions, and a plurality of second word lines located along diverging portions of the first word line, comprising: applying a positive voltage to a first word line corresponding to the memory cell whose stored signal is read out; applying a zero voltage to other first word lines; applying a zero voltage to second word lines corresponding to said memory cell whose stored signal is read out; applying a negative voltage to other second word lines, thereby canceling the positive voltage applied to the first word line corresponding to the memory cell whose stored signal is read out; and outputting the stored signal from the bit lines corresponding to the memory cell whose stored signal is read out.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-07 | 1998-05-09 | 1998-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-07 | 2002-05-09 | 2002-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-07 | 2006-05-09 | 2006-11-08 | $7700.00 | Window Closed / Lapsed |