US5363319A
Expired / Lapsed
US
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Logic simulator
Assignee: Toshiba Corp
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Filing: 1991-09-27
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Granted: 1994-11-08
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Expires: 2011-09-27
Abstract
Abstract A logic simulator having plural logic function sections for realizing a logic circuit, plural connection sections for connecting these logic function sections, a control section for constructing a logic simulation circuit by controlling these logic function sections and connection sections, and a host computer as an interface and a controller of the logic simulator. Each logic element includes a memory for storing information to decide a logic function, another memory for storing other control information. A logic element having a PLA where each logic to be realized is developed by an AND plane and the result is obtained through an OR plane based on predetermined information. A logic element having a universal logic gate, the input terminals of the universal logic gate being respectively connected to the input terminals of the logic element through plural switches. A unit-delay multiples logic element having a sampling hold circuit including a specification section for specifying only one pulse signal from a multiplexed input signal, a sampling section for sampling a pulse signal specified by the specification section at a predetermined simulation cycle, and a hold section for holding a pulse signal sampled by the sampling section and converting the pulse signal into a restoration signal having a constant level at start of a new simulation cycle, a logic circuit for giving a predetermined logic operation to the restoration signal, and a pulse circuit for producing a multiplexable pulse signal from a signal processed by the logic circuit.
Inventors
- 👤 Nobuo Okuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:55
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
145 words
A logic simulator comprising: a plurality of stages each having a plurality of logic function sections for realizing functions equivalent to a circuit to be simulated; a plurality of connection sections for connecting these logic function sections; a plurality of memory means to receive inputs indicative of data and control information; a control section for constructing a simulation circuit by controlling said logic function sections and connection sections so as to execute logic simulation by said simulation circuit; holding means for creating connections of logical switching elements prior to the execution of said logic simulation; stopping means for stopping a logic simulation upon receipt of an interruption signal produced by an individual logic element; and a host computer for serving as an interface to a designer and for providing a means by which the designer can input the design of the circuit to be simulated.
Claim 2
Dependent Claim
145 words
A logic simulator comprising: a plurality of stages each having a plurality of logic function sections for realizing functions equivalent to a circuit to be simulated; a plurality of connection sections for connecting these logic function sections; a plurality of memory means to receive inputs indicative of data and control information; a control section for constructing a simulation circuit by controlling said logic function sections and connection sections so as to execute logic simulation by said simulation circuit; holding means for creating connections of logical switching elements prior to the execution of said logic simulation; stopping means for stopping a logic simulation upon receipt of an interruption signal produced by an individual logic element; and a host computer for serving as an interface to a designer and for providing a means by which the designer can input the design of the circuit to be simulated.
Claim 3
Dependent Claim
39 words
The logic simulator according to claim 1, wherein each logic function section comprises a plurality of logic elements having functions equivalent to one of a combinational circuit or a sequential circuit and connection elements for connecting these logic elements.
Claim 4
Dependent Claim
96 words
The logic simulator according to claim 2, wherein each logic element comprises data memory means for storing data equivalent to data to be outputted from an optional logic circuit and control information memory means for storing control information to control the logic element, so that the logic element receives a signal outputted from a logic element on the previous stage as an address signal, holds data stored at an address in the data memory means designated by the address signal based on the control information from the control information memory means, and outputs a unit-delay signal.
Claim 5
Dependent Claim
61 words
The logic simulator according to claim 2, wherein The connection section and connection element respectively comprise a plurality of connection lines, switching elements respectively placed on these connection lines, and hold means for holding information to control ON/OFF of each switching element, so that each connection line is connected or disconnected based on the control information held in the hold means.
Claim 6
Dependent Claim
83 words
The logic simulator according to claim 2, wherein each logic element includes a universal logic gate, the input terminals of the universal logic gate being respectively connected to the input terminals of the logic element through a plurality of switches so as to realize a predetermined logic function with a function of the logic element by changing connection relation between the input terminals of the universal logic gate and the input terminals of the logic element by suitable ON/OFF operation of these switches.
Claim 7
Dependent Claim
99 words
The logic simulator according to claim 2, wherein each of logic elements includes memory means for storing information to decide a logic function and memory means for storing other control information, and having a programmable logic array (PLA) circuit which is so constructed as to develop each logic corresponding to input signals with an AND plane and selectively obtain the output of the AND plane through an OR plane based on the information given in advance to the memory means in accordance with truth values of a logic circuit to be realized, in order to output a unit-delay signal.
Claim 8
Dependent Claim
160 words
A unit-delay multiplexed logic element, comprising: sampling hold means corresponding to each multiplex input signal, which includes: sampling signal generating means for generating a signal to sample only a specific pulse signal from a multiplex input signal, sampling means for sampling the specific pulse signal sampled by the sampling signal generating means in a predetermined simulation cycle, and hold means for holding the specific pulse signal sampled by the sampling means, and converting the signal start of the new simulation cycle into a restoration signal having a constant level during the new simulation cycle; an ordinary logic circuit for outputting a logic output signal produced by giving a predetermined logic operation to the restoration signal outputted from the sampling hold means; and pulse means for sampling the output of said ordinary logic circuits output signal at a predetermined timing and outputting an operated multiplexable pulse signal only in response to said specific pulse signal from said sampling signal generating means.
Claim 9
Dependent Claim
160 words
A unit-delay multiplexed logic element, comprising: sampling hold means corresponding to each multiplex input signal, which includes: sampling signal generating means for generating a signal to sample only a specific pulse signal from a multiplex input signal, sampling means for sampling the specific pulse signal sampled by the sampling signal generating means in a predetermined simulation cycle, and hold means for holding the specific pulse signal sampled by the sampling means, and converting the signal start of the new simulation cycle into a restoration signal having a constant level during the new simulation cycle; an ordinary logic circuit for outputting a logic output signal produced by giving a predetermined logic operation to the restoration signal outputted from the sampling hold means; and pulse means for sampling the output of said ordinary logic circuits output signal at a predetermined timing and outputting an operated multiplexable pulse signal only in response to said specific pulse signal from said sampling signal generating means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-07 | 1998-05-09 | 1998-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-07 | 2002-05-09 | 2002-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-07 | 2006-05-09 | 2006-11-08 | $7700.00 | Window Closed / Lapsed |