Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines

Claim 1

A circuit for addressing a random access memory (RAM) device having x address lines divided into two sets of address lines, column address lines and row address lines, comprising: an x bit counter having y least significant bits, z most significant bits, and n intermediate bits, where y+z+n=x, said y and z bits being further divided into least significant bits and most significant bits, where x, y, z and n are positive integers, a first multiplexer having A and B inputs and an output, the A input coupled to said y bits, the B input coupled to said z bits, a second multiplexer having A and B inputs and an output the A input of said second multiplexer coupled to said z bits and the B input of said second multiplexer coupled to said y bits, and a register having y+n+z input lines and output lines, the y least significant of said input lines of said register coupled to said output of said first multiplexer, the n intermediate input lines of said register coupled to said n intermediate bits of said counter and the z most significant of said input lines of said register coupled to said output of said second multiplexer, and having the least significant bits of said first and second multiplexer outputs coupled to said column address lines and having the most significant bits of said first and second multiplexer outputs coupled to said row address lines.