Graphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile size

Claim 2

A graphics system for storing pixel data values into addressable pixel locations of a frame buffer from whence an image can be displayed, the graphics system comprising: rendering means for computing pixel addresses corresponding to cartesian coordinates of physical locations of individual pixels upon a display and for computing pixel values describing an image to be displayed; and tile definition means, coupled to the pixel addresses and to the pixel values, for defining tiles composed of bounded regions containing contiguous pixel locations, and for producing at an output having less than the number of signal lines needed to simultaneously transmit a complete pixel address and an associated pixel value and coupled to a frame buffer: (a) the complete pixel address in alternation with its associated pixel value when the pixel lies within a different tile than that which contained the preceding pixel; and (b) a subset of the pixel address concurrently with its associated pixel value when the pixel is within the boundaries of the same tile that contained the preceding pixel.

Claim 3

A graphics system as in claim 1 wherein the subset of the pixel address comprises some number of least significant bits of the complete pixel address.

Claim 4

A graphics system as in claim 1 wherein the pixel addresses represent abscissa/ordinate pairs referenced to an origin and wherein the tile definition means determines tile boundaries by partitioning the abscissa into groups of m-many consecutive abscissa values and by partitioning the ordinate into groups of n-many consecutive ordinate values.

Claim 5

A graphics system as in claim 3 wherein m and n are selectable within the ranges 1<=m<=M and 1<=n<N, where M and N are preselected integers.

Claim 6

A graphics system as in claim 3 wherein the subset of the pixel address includes an abscissa portion of bits, j in number, 2>=m, and an ordinate portion of bits, k in number, 2>=n.

Claim 7

Apparatus for generating pixel addresses and pixel values used in storing a graphics image into a frame buffer, from whence it can later be displayed, the apparatus comprising: first register means for storing a next pixel value; second register means for storing an abscissa portion of a next pixel address; third register means for storing an ordinate portion of the next pixel address; fourth register means, coupled to the second register means, for storing the abscissa portion of a previous pixel address; fifth register means, coupled to the third register means, for storing the ordinate portion of the previous pixel value; first comparison means, coupled to the fourth register means and to the abscissa portion of the next pixel address, for generating a first comparison signal whenever the content of the fourth register means and the abscissa portion of the next pixel address differ in other than a first selected number of least significant bits; second comparison means, coupled to the fifth register means and to the ordinate portion of the next pixel address, for generating a second comparison signal whenever the content of the fifth register means and the ordinate portion of the next pixel address differ in other than a second selected number of least significant bits; logic means, coupled to the first and second comparison signals, for producing a NEW TILE signal indicative of the occurrence of at least one of the first and second comparison signals and a NEW PIXEL signal whenever the NEW TILE signal is absent subsequent to a comparison by the first and second comparison means; and output means, coupled to the first, second and third register means, as well as to the NEW TILE and NEW PIXEL signals, for outputting onto a bus: (a) a pixel address for a next pixel having a complete abscissa portion and a complete ordinate portion in alternation with the associated pixel value whenever the signal NEW TILE occurs; and (b) a pixel address for a next pixel having a subset of the abscissa portion and a subset of the ordinate portion concurrently with the associated pixel value whenever the signal NEW PIXEL occurs.

Claim 8

Apparatus for generating pixel addresses and pixel values used in storing a graphics image into a frame buffer, from whence it can later be displayed, the apparatus comprising: first register means for storing a next pixel value; second register means for storing an abscissa portion of a next pixel address; third register means for storing an ordinate portion of the next pixel address; fourth register means, coupled to the second register means, for storing the abscissa portion of a previous pixel address; fifth register means, coupled to the third register means, for storing the ordinate portion of the previous pixel value; first comparison means, coupled to the fourth register means and to the abscissa portion of the next pixel address, for generating a first comparison signal whenever the content of the fourth register means and the abscissa portion of the next pixel address differ in other than a first selected number of least significant bits; second comparison means, coupled to the fifth register means and to the ordinate portion of the next pixel address, for generating a second comparison signal whenever the content of the fifth register means and the ordinate portion of the next pixel address differ in other than a second selected number of least significant bits; logic means, coupled to the first and second comparison signals, for producing a NEW TILE signal indicative of the occurrence of at least one of the first and second comparison signals and a NEW PIXEL signal whenever the NEW TILE signal is absent subsequent to a comparison by the first and second comparison means; and output means, coupled to the first, second and third register means, as well as to the NEW TILE and NEW PIXEL signals, for outputting onto a bus: (a) a pixel address for a next pixel having a complete abscissa portion and a complete ordinate portion in alternation with the associated pixel value whenever the signal NEW TILE occurs; and (b) a pixel address for a next pixel having a subset of the abscissa portion and a subset of the ordinate portion concurrently with the associated pixel value whenever the signal NEW PIXEL occurs.