US4694288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiwindow display circuit
Assignee: Sharp Corp
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Filing: 1984-09-05
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Granted: 1987-09-15
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Expires: 2004-09-05
Abstract
Abstract A multiwindow display circuit comprises a horizontal boundary memory for storing horizontal boundary data of display windows, a vertical boundary memory for storing vertical boundary data of the display windows, a display address memory for storing an address of each of the display windows, a picture information memory for storing picture information related to the address stored within the display address memory, a bias value memory for storing bias values for the display windows, an address converter for adding a selected one of the bias values to the address of the display address memory to convert the display address, a window select circuit for selecting a single window from among the display windows, a display timing controller for changing a code representative of the single window, and a display responsive to the display timing controller for displaying any portion of the picture information memory in any area of the display.
Inventors
- 👤 Munenori Harada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:10
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/14
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
331 words
A multiwindow display circuit comprising: display means for displaying a plurality of display windows; horizontal frame memory means for storing horizontal boundary data for each one of said plurality of display windows; vertical frame memory means for storing vertical boundary data for each one of said plurality of display windows; display address means for sequentially producing an initial address for each one of said plurality of display windows; picture information memory means for storing picture information corresponding to each said initial address; window selection means, responsive to said horizontal frame memory means and said vertical frame memory means, for selecting a particular display window from said plurality of display windows, said particular display window being selected when said initial address data is determined by said window selection means to be in said horizontal and vertical boundary data for said particular display window; bias value memory means for storing a plurality of bias values for each one of said plurality of display windows, each one of said bias values representing the boundary data defined by said horizontal frame memory means and said vertical frame memory means of said window selection means; address converter means for adding a selected one of said bias values corresponding to the selected display window to said initial address produced by said display address means to obtain a desired display address, said desired display address then being provided to said picture information memory means to access corresponding picture information; and display timing control means, responsive to said window selection means, for providing a code representative of the selected display window to said display means for directing the display of said selected window, and controlling the supply of accessed picture information to said display means; said display means being responsive to said code provided by said display timing means and said supplied picture information, whereby any portion of said picture information stored in said picture information memory means can be displayed on any display window of said display means.
Claim 2
Dependent Claim
331 words
A multiwindow display circuit comprising: display means for displaying a plurality of display windows; horizontal frame memory means for storing horizontal boundary data for each one of said plurality of display windows; vertical frame memory means for storing vertical boundary data for each one of said plurality of display windows; display address means for sequentially producing an initial address for each one of said plurality of display windows; picture information memory means for storing picture information corresponding to each said initial address; window selection means, responsive to said horizontal frame memory means and said vertical frame memory means, for selecting a particular display window from said plurality of display windows, said particular display window being selected when said initial address data is determined by said window selection means to be in said horizontal and vertical boundary data for said particular display window; bias value memory means for storing a plurality of bias values for each one of said plurality of display windows, each one of said bias values representing the boundary data defined by said horizontal frame memory means and said vertical frame memory means of said window selection means; address converter means for adding a selected one of said bias values corresponding to the selected display window to said initial address produced by said display address means to obtain a desired display address, said desired display address then being provided to said picture information memory means to access corresponding picture information; and display timing control means, responsive to said window selection means, for providing a code representative of the selected display window to said display means for directing the display of said selected window, and controlling the supply of accessed picture information to said display means; said display means being responsive to said code provided by said display timing means and said supplied picture information, whereby any portion of said picture information stored in said picture information memory means can be displayed on any display window of said display means.
Claim 3
Dependent Claim
28 words
The circuit of claim 1, wherein said display timing control means includes control means, responsive to said code, for reversing or blinking the selected said particular display window.
Claim 4
Dependent Claim
59 words
The circuit of claim 1, wherein said address converter means includes multiplexer means, responsive to said horizontal frame memory means, said vertical frame memory means, said display address means, and said bias value memory, for selecting one of said bias values in said bias value memory to be added to said initial address produced by said display address means.
Claim 5
Dependent Claim
24 words
The circuit of claim 1, further comprising priority means for selecting between overlapping said display windows based upon the priority of said display windows.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-14 | 1991-03-16 | 1991-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-14 | 1995-03-16 | 1995-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-14 | 1999-03-16 | 1999-09-15 | $7700.00 | Window Closed / Lapsed |