US5289279A
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Video signal data recoding method for standard memory components and apparatus for perfomring the method
Assignee: Siemens AG
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Filing: 1990-07-16
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Granted: 1994-02-22
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Expires: 2010-07-16
Abstract
Abstract A method for storing video signal data of at least a partial frame in standard memory components includes providing standard memory components with 2 m possible memory addresses, addressing b pixels with x address bits and separately addressing z lines with y address bits through picture addresses, and selecting b<2 x , z<2 y , and m, b, z, x and y as positive integers 2 m is selected to be as small as possible but greater than the product of b and z. The x address bits and y address bits are recoded utilizing bit combinations not occurring in the picture addresses for uniquely assigning each occurring picture address its own memory address. A circuit configuration for performing the method includes a memory device having memory address input terminals for addressing 2 m possible memory addresses, a data input terminal, and a data output terminal. A control device assigns picture addresses to video signal data and controls memorization of the video signal data. The control device has picture address terminals carrying picture addresses with separate x address bits for pixel addressing and y address bits for line addressing. A recoding apparatus is connected between the picture address terminals and the memory address input terminals for uniquely assigning each picture address its own memory address. A device is provided for reading out video signal data from the memory device.
Inventors
- 👤 Bodo Braun
- 👤 Erich-Johann Bayer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:44
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/907; G; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
111 words
Method for storing video signal data of at least a partial frame in standard memory components, which comprises providing standard memory components with 2 m possible memory addresses; addressing b pixels with x address bits and separately addressing z lines with y address bits through picture addresses; selecting b<2 x ; selecting z<2 y ; selecting m, b, z, x and y as positive integers; selecting 2 m as small as possible but greater than the product of b and z; and recoding the x address bits and y address bits utilizing bit combinations not occurring in the picture addresses for uniquely assigning each occurring picture address its own memory address.
Claim 2
Dependent Claim
111 words
Method for storing video signal data of at least a partial frame in standard memory components, which comprises providing standard memory components with 2 m possible memory addresses; addressing b pixels with x address bits and separately addressing z lines with y address bits through picture addresses; selecting b<2 x ; selecting z<2 y ; selecting m, b, z, x and y as positive integers; selecting 2 m as small as possible but greater than the product of b and z; and recoding the x address bits and y address bits utilizing bit combinations not occurring in the picture addresses for uniquely assigning each occurring picture address its own memory address.
Claim 3
Dependent Claim
15 words
Method according to claim 1, which comprises performing the recoding step with an image matrix.
Claim 4
Dependent Claim
26 words
Method according to claim 1, which comprises controlling the recoding step with at least one bit from the group of the x and y address bits.
Claim 5
Dependent Claim
48 words
Method according to claim 1, which comprises recoding only s address bits of the x address bits and r address bits of the y address bits into p address bits of the memory addresses, selecting s, r and p as positive integers, and selecting: s<x, r<y, and p<s+r.
Claim 6
Dependent Claim
13 words
Method according to claim 1, which comprises serially multiplexing the video signal data.
Claim 7
Dependent Claim
23 words
Method according to claim 1, which comprises storing, at least 768 pixels per line and at least 288 lines in the standard memory.
Claim 8
Dependent Claim
15 words
Method according to claim 1, which comprises storing a half frame in the standard memory.
Claim 9
Dependent Claim
15 words
Method according to claim 1, which comprises storing a full frame in the standard memory.
Claim 10
Dependent Claim
47 words
Method according to claim 1, which comprises storing video signal data with bit plane interlacing, and selecting a number of memory words per line approximately from a number of data words per line, multiplied by a ratio between a data word width and a memory word width.
Claim 11
Dependent Claim
129 words
Circuit configuration for storing video signal data of at least a partial frame in standard memory components having 2 m possible memory addresses, comprising: a memory device having memory address input terminals for addressing 2 m possible memory addresses, a data input terminal, and a data output terminal; a control device for assigning picture addresses to video signal data and controlling memorization of the video signal data, said control device having picture address terminals carrying picture addresses with separate x address bits for pixel addressing and y address bits for line addressing; a recoding apparatus connected between said picture address terminals and said memory address input terminals for uniquely assigning each picture address its own memory address; and means for reading out video signal data from said memory device.
Claim 12
Dependent Claim
129 words
Circuit configuration for storing video signal data of at least a partial frame in standard memory components having 2 m possible memory addresses, comprising: a memory device having memory address input terminals for addressing 2 m possible memory addresses, a data input terminal, and a data output terminal; a control device for assigning picture addresses to video signal data and controlling memorization of the video signal data, said control device having picture address terminals carrying picture addresses with separate x address bits for pixel addressing and y address bits for line addressing; a recoding apparatus connected between said picture address terminals and said memory address input terminals for uniquely assigning each picture address its own memory address; and means for reading out video signal data from said memory device.
Claim 13
Dependent Claim
22 words
Circuit configuration of claim 10, wherein said recoding apparatus has multiplexers being controlled by at least one bit of the picture addresses.
Claim 14
Dependent Claim
134 words
Method for storing video signal data of at least a partial frame in standard memory components, which comprises providing standard memory components with 2 m possible memory addresses; addressing b pixels with x address bits through picture addresses; selecting b<2 x ; selecting z<2 y ; selecting m, b, z, x and y as positive integers; selecting 2 m as small as possible but greater than the product of b and z; recoding a address bits of the x address bits and r address bits of the y address bits into p address bits of the memory addresses utilizing bit combinations not occurring in the picture addresses for uniquely assigning each occurring picture address its own memory address, and selecting: s<x and r<y and p<s+r and selecting s, r, and p as positive integers.
Claim 15
Dependent Claim
134 words
Method for storing video signal data of at least a partial frame in standard memory components, which comprises providing standard memory components with 2 m possible memory addresses; addressing b pixels with x address bits through picture addresses; selecting b<2 x ; selecting z<2 y ; selecting m, b, z, x and y as positive integers; selecting 2 m as small as possible but greater than the product of b and z; recoding a address bits of the x address bits and r address bits of the y address bits into p address bits of the memory addresses utilizing bit combinations not occurring in the picture addresses for uniquely assigning each occurring picture address its own memory address, and selecting: s<x and r<y and p<s+r and selecting s, r, and p as positive integers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |