US5083121A
Expired / Lapsed
US
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System for maximizing utilization of a display memory
Assignee: Sharp Corp
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Filing: 1989-10-03
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Granted: 1992-01-21
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Expires: 2009-10-03
Abstract
Abstract A system for maximized utilization of a display memory of a type including 2 n memory elements of equal storage capacity arranged in a block fashion in corespondence with a display screen, each memory element being capable of storing, in a two-dimensional address, the pixel data which includes a predetermined number of bits. The system includes 2 n-m memory groups, each includes 2 m memory elements neighboring with each other on the display screen, an RAS switch connected between an RAS signal line and an RAS terminal of each of the memory elements forming each memory group, and a CAS switch connected between a CAS signal line and a CAS terminal of each of the memory elements forming each memory group. Thus, they can be switched over on a hardware basis to allow the reading of the pixel data from the display memory to be compatible with either one of a monochromatic and color display device, or one of a vertically and horizontally longer display device.
Inventors
- 👤 Akihiro Nomura
- 👤 Toshimi Kiyohara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:43
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/395; G06; G06F; G06F3/00; G06F3/14; G06F3/1423
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
284 words
A system for maximizing utilization of a display memory of a type including 2 n (n being an integer) memory elements of equal storage capacity arranged in a block fashion in correspondence with a display screen, each of the memory elements being capable of storing at least one color pixel data which includes a predetermined number of bits in a two-dimensional address, the system comprising: 2 n-m (m being an integer, wherein n>m) memory groups, each including 2 m memory elements neighboring each other in a horizontal direction with respect to the display screen; Row Address Strobe (RAS) switching means, connected between an RAS signal line and an RAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups; and Column Address Strobe (CAS) switching means, connected between a CAS signal line and a CAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups, whereby, when the display in color representation is desired, the RAS switching means is concurrently connected with all of the RAS terminals of the 2 m memory elements and the CAS switching means is sequentially switched over to selectively connect with each of the CAS terminals of the 2 m memory elements, and, when the display in monochromatic representation is desired, the CAS switching means is concurrently connected with all of the CAS terminals of the 2 m memory elements and the RAS switching means is sequentially switched over to selectively connect with each of the RAS terminals of the 2 m memory elements, to thereby permit the display memory to be efficiently utilized for the selective display in color representation and in monochromatic representation.
Claim 2
Independent Claim
284 words
A system for maximizing utilization of a display memory of a type including 2 n (n being an integer) memory elements of equal storage capacity arranged in a block fashion in correspondence with a display screen, each of the memory elements being capable of storing at least one color pixel data which includes a predetermined number of bits in a two-dimensional address, the system comprising: 2 n-m (m being an integer, wherein n>m) memory groups, each including 2 m memory elements neighboring each other in a horizontal direction with respect to the display screen; Row Address Strobe (RAS) switching means, connected between an RAS signal line and an RAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups; and Column Address Strobe (CAS) switching means, connected between a CAS signal line and a CAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups, whereby, when the display in color representation is desired, the RAS switching means is concurrently connected with all of the RAS terminals of the 2 m memory elements and the CAS switching means is sequentially switched over to selectively connect with each of the CAS terminals of the 2 m memory elements, and, when the display in monochromatic representation is desired, the CAS switching means is concurrently connected with all of the CAS terminals of the 2 m memory elements and the RAS switching means is sequentially switched over to selectively connect with each of the RAS terminals of the 2 m memory elements, to thereby permit the display memory to be efficiently utilized for the selective display in color representation and in monochromatic representation.
Claim 3
Dependent Claim
64 words
The system of claim 1, wherein, the RAS switching means is concurrently connected with all of the RAS terminals of the 2 m memory elements and the CAS switching means is sequentially switched over to selectively connect with each of the CAS terminals of the 2 m memory elements, sequentially, for each of the 2 n-m memory groups, corresponding to a video raster scan.
Claim 4
Dependent Claim
64 words
The system of claim 1, wherein, the CAS switching means is concurrently connected with all of the CAS terminals of the 2 m memory elements and the RAS switching means is sequentially switched over to selectively connect with each of the RAS terminals of the 2 m memory elements, sequentially, for each of the 2 n-m memory groups, corresponding to a video raster scan.
Claim 5
Independent Claim
336 words
A system for maximizing utilization of a display memory of a type including 2 n (n being an integer) memory elements of equal storage capacity arranged in a block fashion in correspondence with a display screen, each of the memory elements being capable of storing at least one color pixel data which includes a predetermined number of bits in a two-dimensional address, the system comprising: 2 n-m (m being an integer, where n>m) memory groups each including 2 m memory elements neighboring each other on the display screen; Row Address Strobe (RAS) switching means, connected between an RAS signal line and an RAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups; and Column Address Strobe (CAS) switching means, connected between a CAS signal line and a CAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups, whereby, when a screen size of the display screen is 2 n-m pixels in a first dimension and 2 m pixels in a second dimension, the RAS switching means is concurrently connected with all of the RAS terminals of the 2 m memory elements and the CAS switching means is sequentially switched over to selectively connect with each of the CAS terminals of the 2 m memory elements and, when the screen size of the display screen is 2 n pixels in the first dimension and 1 pixel in the second direction, the CAS switching means is connected with all of the CAS terminals of the 2 m memory elements and the RAS switching means is sequentially switched over to selectively connect with each of the RAS terminals of the 2 m memory elements, to thereby permit the display memory to be efficiently utilized for the selective display on the display unit of a screen size longer in the first dimension than in the second, and on the display unit of a screen size longer in the second dimension than in the first.
Claim 6
Independent Claim
336 words
A system for maximizing utilization of a display memory of a type including 2 n (n being an integer) memory elements of equal storage capacity arranged in a block fashion in correspondence with a display screen, each of the memory elements being capable of storing at least one color pixel data which includes a predetermined number of bits in a two-dimensional address, the system comprising: 2 n-m (m being an integer, where n>m) memory groups each including 2 m memory elements neighboring each other on the display screen; Row Address Strobe (RAS) switching means, connected between an RAS signal line and an RAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups; and Column Address Strobe (CAS) switching means, connected between a CAS signal line and a CAS terminal of each of the 2 m memory elements forming each of the 2 n-m memory groups, whereby, when a screen size of the display screen is 2 n-m pixels in a first dimension and 2 m pixels in a second dimension, the RAS switching means is concurrently connected with all of the RAS terminals of the 2 m memory elements and the CAS switching means is sequentially switched over to selectively connect with each of the CAS terminals of the 2 m memory elements and, when the screen size of the display screen is 2 n pixels in the first dimension and 1 pixel in the second direction, the CAS switching means is connected with all of the CAS terminals of the 2 m memory elements and the RAS switching means is sequentially switched over to selectively connect with each of the RAS terminals of the 2 m memory elements, to thereby permit the display memory to be efficiently utilized for the selective display on the display unit of a screen size longer in the first dimension than in the second, and on the display unit of a screen size longer in the second dimension than in the first.
Claim 7
Dependent Claim
64 words
The system of claim 4, wherein, the RAS switching means is concurrently connected with all of the RAS terminals of the 2 m memory elements and the CAS switching means is sequentially switched over to selectively connect with each of the CAS terminals of the 2 m memory element, sequentially, for each of the 2 n-m memory groups, corresponding to a video raster scan.
Claim 8
Dependent Claim
64 words
The system of claim 4, wherein, the CAS switching means is concurrently connected with all of the CAS terminals of the 2 m memory elements and the RAS switching means is sequentially switched over to selectively connect with each of the RAS terminals of the 2 m memory elements, sequentially, for each of the 2 n-m memory groups, corresponding to a video raster scan.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-20 | 1995-07-22 | 1996-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-20 | 1999-07-22 | 2000-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-20 | 2003-07-22 | 2004-01-21 | $7700.00 | Window Closed / Lapsed |