US4533909A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer with color display
Assignee: Apple Inc
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Filing: 1983-12-12
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Granted: 1985-08-06
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Expires: 2003-12-12
Abstract
Abstract A microcomputer system with video display capability, particularly suited for small business applications and home use is described. The CPU performance is enhanced by permitting zero page data to be stored throughout the memory. The circuitry permitting this capability also provides a pointer for improved direct memory access. Through unique circuitry resembling "bank switching" improved memory mapping is obtained. 4-bit digital signals are converted to an AC chroma signal and a separate luminance signal for display modes. Display modes include high resolution modes, one of which displays 80 characters per line.
Inventors
- 👤 Wendell B. Sander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G09; G09G; G09G1/00; G09G1/28; G09G1/285; G09G5/00; G09G5/22; G09G5/222
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
110 words
In a digitally controlled, raster scanned, video display for use with a microcomputer, or the like, which display provides color images in response to chroma signals having predetermined phase relationships to a reference signal of frequency (f), a circuit for providing a digitally controlled chroma signal comprising: digital word generation means for generating predetermined digital signals; serializing means coupled to said generation means for repeating said word in a serial form at a predetermined frequency so as to provide frequency components at said frequency f; converting means, coupled to said serializing means for converting outputs from said serializing means to an AC signal; whereby a video chroma signal is generated.
Claim 2
Dependent Claim
110 words
In a digitally controlled, raster scanned, video display for use with a microcomputer, or the like, which display provides color images in response to chroma signals having predetermined phase relationships to a reference signal of frequency (f), a circuit for providing a digitally controlled chroma signal comprising: digital word generation means for generating predetermined digital signals; serializing means coupled to said generation means for repeating said word in a serial form at a predetermined frequency so as to provide frequency components at said frequency f; converting means, coupled to said serializing means for converting outputs from said serializing means to an AC signal; whereby a video chroma signal is generated.
Claim 3
Dependent Claim
23 words
The circuit defined by claim 1 including additional circuit means coupled to said digital word generation means for providing a DC luminance signal.
Claim 4
Dependent Claim
24 words
The circuit defined by claim 1 wherein said digital words are coupled to a resistive weighting network for providing a gray scale video signal.
Claim 5
Dependent Claim
22 words
The circuit defined by claim 1 wherein said digital words are 4-bit words and wherein said predetermined frequency is equal to 4f.
Claim 6
Dependent Claim
22 words
The circuit defined by claim 4 wherein said serializing means comprises a multiplexer which is controlled in sychronization with said frequency f.
Claim 7
Dependent Claim
20 words
The circuit defined by claim 5 wherein said converting means includes an inverter coupled to an output of said multiplexer.
Claim 8
Dependent Claim
23 words
The circuit defined by claim 6 including additional circuit means coupled to said digital word generation means for providing a DC luminance signal.
Claim 9
Dependent Claim
82 words
The circuit defined by claim 1 wherein said digital word generation means comprises: a source of digital data for controlling said display; a first register coupled to receive data from said source of data; a multiplexer for selecting between two buses, the output of said multiplexer coupled to said serializing means, said buses coupled to said first register, a shift register coupled to receive data from said source of data, said shift register providing a serialized digital signal for controlling said multiplexer.
Claim 10
Dependent Claim
39 words
The circuit defined by claim 8 including a character memory for storing data representative of alpha numeric characters, said memory coupled to receive address from said source of data, the output of said memory coupled to said shift register.
Claim 11
Dependent Claim
35 words
The circuit defined by claim 9 wherein when said first register is disabled, one of said two buses is clamped to provide all binary ones, and the other of said buses provides all binary zeros.
Claim 12
Dependent Claim
27 words
The circuit defined by claim 10 wherein said shift register is controlled by a plurality of clocking signals, all of which are synchronized with said frequency f.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-05 | 1989-02-04 | 1989-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-05 | 1993-02-04 | 1993-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-05 | 1997-02-04 | 1997-08-06 | $7700.00 | Window Closed / Lapsed |