US5360981A — Amorphous silicon memory

Claim 1

Independent Claim 162 words

An analog memory device capable of being set and reset to a resistance value over a continuous range of resistance values which is a measure of a voltage applied to it over a corresponding range of voltage values, said analog memory device comprising: a first conducting layer (a); a single thin layer (b) in direct electrical contact with layer (a); a metal top contact (c) in electrical contact with layer (b) without interposition of an intermediate conductive layer, the metal being one of V, Co, Ni, Pd, Fe or Mn; wherein layer (b) exhibits said range of resistance values and is located between layer (a) and layer (c), said layer (b) being formed by one of (i) pure or doped amorphous silicon, (ii) pure or doped amorphous hydrogenated silicon or (iii) a hydrogenated silicon alloy; and wherein layer (b) has been subjected to a voltage sufficiently high to convert it into an analog memory device exhibiting said range of settable resistance values.

Claim 2

Dependent Claim 162 words

An analog memory device capable of being set and reset to a resistance value over a continuous range of resistance values which is a measure of a voltage applied to it over a corresponding range of voltage values, said analog memory device comprising: a first conducting layer (a); a single thin layer (b) in direct electrical contact with layer (a); a metal top contact (c) in electrical contact with layer (b) without interposition of an intermediate conductive layer, the metal being one of V, Co, Ni, Pd, Fe or Mn; wherein layer (b) exhibits said range of resistance values and is located between layer (a) and layer (c), said layer (b) being formed by one of (i) pure or doped amorphous silicon, (ii) pure or doped amorphous hydrogenated silicon or (iii) a hydrogenated silicon alloy; and wherein layer (b) has been subjected to a voltage sufficiently high to convert it into an analog memory device exhibiting said range of settable resistance values.

Claim 3

Dependent Claim 17 words

An analog memory device as in claim 1, wherein layer (b) is formed of doped amorphous silicon.

Claim 4

Dependent Claim 21 words

An analog memory device as in claim 1, wherein the metal of the top contact is V, Co, Ni or Pd.

Claim 5

Independent Claim 152 words

A method of making an analog memory device capable of being set and rest into a resistance over a continuous range of more than two resistance values which is a measure of a voltage applied to it over a corresponding range of voltage values, said method comprising the steps of: (i) depositing a first conducting layer (a) directly on an insulating substrate; (ii) depositing a thin layer (b) of one of (i) pure or doped amorphous silicon, (ii) pure or doped amorphous hydrogenated silicon or (iii) a hydrogenated silicon alloy on layer (a); (iii) depositing a contact layer (c) of V, Co, Ni, Pd, Fe or Mn on layer (b) without interposition of an intermediate conductive layer; (iv) applying a first forming voltage to the device, said voltage being sufficient to permanently reduce the resistance of the device; and (v) applying a second voltage to further reduce the resistance of the element.

Claim 6

Independent Claim 152 words

A method of making an analog memory device capable of being set and rest into a resistance over a continuous range of more than two resistance values which is a measure of a voltage applied to it over a corresponding range of voltage values, said method comprising the steps of: (i) depositing a first conducting layer (a) directly on an insulating substrate; (ii) depositing a thin layer (b) of one of (i) pure or doped amorphous silicon, (ii) pure or doped amorphous hydrogenated silicon or (iii) a hydrogenated silicon alloy on layer (a); (iii) depositing a contact layer (c) of V, Co, Ni, Pd, Fe or Mn on layer (b) without interposition of an intermediate conductive layer; (iv) applying a first forming voltage to the device, said voltage being sufficient to permanently reduce the resistance of the device; and (v) applying a second voltage to further reduce the resistance of the element.

Claim 7

Dependent Claim 34 words

A method as in claim 4 wherein the first forming voltage is 13-14 volts, the second forming voltage is 1-2 volts higher than the first forming voltage and layer (b) is 20-350 nm thick.

Claim 8

Dependent Claim 45 words

A neural network structure including a plurality of analog memory devices as in claim 1 wherein said neural network structure comprises an insulating substrate having deposited thereon a plurality of said analog memory devices wherein each layer (a) is in contact with said insulating substrate.

Claim 9

Dependent Claim 150 words

An analog memory device for use in a neural network as a variable resistance element that can be set and reset to any resistance within a continuous range of resistance values as a function of voltage applied thereto, said analog memory device comprising: a single layer of amorphous silicon grown directly over a first electrical contact layer; a second electrical contact layer of V, Co, Ni, Pd, Fe or Mn grown over said single layer of amorphous silicon without interposition of an intermediate conductive layer; said single layer of amorphous silicon being altered after growth thereof by application of a forming voltage sufficient to convert this layer into a variable resistance element that can thereafter be reliably set and reset to retain any resistance within a continuous range of resistance values as a function of voltage applied thereto until subsequently again set or reset to a different value of resistance.

Claim 10

Dependent Claim 150 words

An analog memory device for use in a neural network as a variable resistance element that can be set and reset to any resistance within a continuous range of resistance values as a function of voltage applied thereto, said analog memory device comprising: a single layer of amorphous silicon grown directly over a first electrical contact layer; a second electrical contact layer of V, Co, Ni, Pd, Fe or Mn grown over said single layer of amorphous silicon without interposition of an intermediate conductive layer; said single layer of amorphous silicon being altered after growth thereof by application of a forming voltage sufficient to convert this layer into a variable resistance element that can thereafter be reliably set and reset to retain any resistance within a continuous range of resistance values as a function of voltage applied thereto until subsequently again set or reset to a different value of resistance.

Claim 11

Dependent Claim 19 words

An analog memory device as in claim 7 wherein said amorphous silicon, except for dopant, is hydrogenated amorphous silicon.

Claim 12

Dependent Claim 17 words

An analog memory device as in claim 7 wherein said amorphous silicon is a hydrogenated silicon alloy.

Claim 13

Dependent Claim 17 words

An analog memory device as in claim 7 wherein said amorphous silicon is a silicon germanium alloy.

Claim 14

Dependent Claim 14 words

An analog memory device as in claim 7 wherein said amorphous silicon contains fluorine.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-10-31	1998-05-02	1998-11-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-10-31	2002-05-02	2002-11-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-10-31	2006-05-02	2006-11-01	$7700.00	Window Closed / Lapsed

Amorphous silicon memory

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