Multilevel sequence of erase pulses for amorphous memory devices

Claim 3

The method of claim 1 wherein said first plurality of reset voltage pulses alternate with said second plurality of reset voltage pulses in said sequence.

Claim 4

The method of claim 1 wherein said first current amplitude is at least twice said second current amplitude.

Claim 5

The method of claim 3 wherein said second current amplitude is at least twice the amplitude of the current produced by said set voltage pulses.

Claim 6

The method of claim 1 wherein said first plurality of reset voltage pulses have a maximum amplitude of no greater than 80 percent of said given threshold voltage value.

Claim 9

The method of claim 6 wherein said first plurality of reset voltage pulses alternate with said second plurality of reset voltage pulses in said sequence.

Claim 10

The method of claim 6 wherein said first current amplitude is at least twice said second amplitude.

Claim 11

The method of claim 8 wherein said second current amplitude is at least twice the amplitude of the current produced by said set voltage pulses.

Claim 12

The method of claim 6 wherein said first plurality of reset voltage pulses have a maximum predetermined magnitude no greater than 80 percent of the maximum threshold value of the memory device.

Claim 13

In a circuit having a filament-type memory device including spaced electrodes between which a body of generally amorphous substantially non-conductive memory semiconductor material which, when a set voltage pulse in excess of a given threshold voltage value and duration is applied to said electrodes has formed therein, a crystalline low resistance filamentous path resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filamentous path to change the phase of the crystalline filament and are of a duration which is so short that upon termination of each reset current pulse the filamentous path will be quickly quenched to leave at least portions of the filamentous path in a substantially amorphous condition; and means connected to said electrodes for applying a sequence of reset voltage pulse or pulses which produces a reset current pulse or pulses which substantially completely convert the crystalline filamentous path to a substantially amorphous filamentous path, the improvement being said means which comprises in first means for applying a first plurality of reset voltage pulses in said sequence having a maximum amplitude below said give threshold voltage value to produce reset current pulses of a first constant amplitude; and a second means for applying a second plurality of reset voltage pulses in said sequence having a maximum amplitude above said given threshold voltge value to produce reset current pulses of a second constant amplitude less than said first constant amplitude.

Claim 14

In a circuit having a filament-type memory device including spaced electrodes between which a body of generally amorphous substantially non-conductive memory semiconductor material which, when a set voltage pulse in excess of a given threshold voltage value and duration is applied to said electrodes has formed therein, a crystalline low resistance filamentous path resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filamentous path to change the phase of the crystalline filament and are of a duration which is so short that upon termination of each reset current pulse the filamentous path will be quickly quenched to leave at least portions of the filamentous path in a substantially amorphous condition; and means connected to said electrodes for applying a sequence of reset voltage pulse or pulses which produces a reset current pulse or pulses which substantially completely convert the crystalline filamentous path to a substantially amorphous filamentous path, the improvement being said means which comprises in first means for applying a first plurality of reset voltage pulses in said sequence having a maximum amplitude below said give threshold voltage value to produce reset current pulses of a first constant amplitude; and a second means for applying a second plurality of reset voltage pulses in said sequence having a maximum amplitude above said given threshold voltge value to produce reset current pulses of a second constant amplitude less than said first constant amplitude.

Claim 15

The circuit of claim 11 wherein said first means and second means apply said first plurality of reset voltage pulses alternate with said second plurality of reset voltage pulses in said sequence respectively.

Claim 16

The circuit of claim 11 wherein said first current amplitude is at least twice said second amplitude.

Claim 17

The circuit of claim 13 wherein said second current amplitude is at least twice the amplitude of the current produced by said set voltage pulses.

Claim 18

The circuit of claim 11 wherein said first plurality of reset voltage pulses have a maximum amplitude of no greater than 80 percent of said given threshold voltage value.

Claim 19

The circuit of claim 11 wherein said first and second means are constant current sources.

Claim 20

In a circuit having a filament-type memory device including spaced electrodes between which extend a body of generally amorphous substantially nonconductive memory semiconductor material which, when a set voltage pulse in excess of a given threshold voltage value and duration is applied to said electrodes, has formed therein a crystalline low resistance filamentous path resettable into a generally amorphous condition by application of one or more voltage pulses producing reset current pulses through said filamentous path which progressively changes the phase of the crystalline filament and returns the same to a generally amorphous state, said progressive phase change of the crystalline filament causing said partially reset filament to have a progressively increasing resistance and threshold voltage value reaching a maximum threshold voltage value when substantially the entire filament is converted to its amorphous condition and means connected to said electrodes for applying a sequence of reset voltage pulses which produce reset current pulses, the improvement being said means which comprises; first means for applying a first plurality of reset voltage pulses having ultimately a given maximum predetermined magnitude less than the maximum threshold voltage value of said memory device to produce reset current pulses of a first amplitude as long as the magnitude of the reset voltage remains in excess of the threshold voltage value of the memory device being reset; and second means for applying a second plurality of reset voltage pulses having ultimately a given maximum predetermined magnitude greter than the maximum threshold voltage values of said memory device to produce reset current pulses of a second amplitude for each of the second plurality of reset voltage pulses.

Claim 21

In a circuit having a filament-type memory device including spaced electrodes between which extend a body of generally amorphous substantially nonconductive memory semiconductor material which, when a set voltage pulse in excess of a given threshold voltage value and duration is applied to said electrodes, has formed therein a crystalline low resistance filamentous path resettable into a generally amorphous condition by application of one or more voltage pulses producing reset current pulses through said filamentous path which progressively changes the phase of the crystalline filament and returns the same to a generally amorphous state, said progressive phase change of the crystalline filament causing said partially reset filament to have a progressively increasing resistance and threshold voltage value reaching a maximum threshold voltage value when substantially the entire filament is converted to its amorphous condition and means connected to said electrodes for applying a sequence of reset voltage pulses which produce reset current pulses, the improvement being said means which comprises; first means for applying a first plurality of reset voltage pulses having ultimately a given maximum predetermined magnitude less than the maximum threshold voltage value of said memory device to produce reset current pulses of a first amplitude as long as the magnitude of the reset voltage remains in excess of the threshold voltage value of the memory device being reset; and second means for applying a second plurality of reset voltage pulses having ultimately a given maximum predetermined magnitude greter than the maximum threshold voltage values of said memory device to produce reset current pulses of a second amplitude for each of the second plurality of reset voltage pulses.

Claim 22

The circuit of claim 17 wherein said first means and second means apply said first plurality of reset voltage pulses alternate with said second plurality of reset voltage pulses in said sequence respectively.

Claim 23

The circuit of claim 17 wherein said first current amplitude is at least twice said second amplitude.

Claim 24

The circuit of claim 19 wherein said second current amplitude is at least twice the amplitude of the current produced by said set voltage pulses.

Claim 25

The circuit of claim 17 wherein said first plurality of reset voltage pulses have a maximum amplitude of no greater than 80 percent of said given threshold voltage value.