Patent US1562900A successfully refreshed from Google Patents.
Patent US5360750A successfully refreshed from Google Patents.
US5360750A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating lateral bipolar transistors
Assignee: United Microelectronics Corp
•
Filing: 1994-01-13
•
Granted: 1994-11-01
•
Expires: 2014-01-13
Abstract
Abstract The present invention discloses a method for manufacturing lateral bipolar transistors of integrated circuits which have expanded collector regions, thereby raising the gain of the lateral bipolar transistors while reducing cycle time for manufacture. As a result, the performance of the transistors is improved and the cost of manufacture is reduced.
Inventors
- 👤 Sheng-Hsing Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:26
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/061; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/096
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
153 words
A method for fabricating NPN lateral bipolar transistors on an N type substrate, which comprises the following steps of: (a) implanting P type impurity into a predetermined position of said substrate and driving in, to form a P well in said substrate; (b) implanting N type impurity into predetermined positions in the P well, to form N - expanded collector regions of said NPN transistors; (c) implanting P type impurity into predetermined positions in the P well, to form contact regions of base electrode of said NPN transistors; (d) implanting N type impurity into predetermined positions in the P well and the N - expanded collector regions, to form emitter electrodes and collector electrodes of said NPN transistors respectively; (e) forming a field oxide layer over said NPN transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said NPN transistors.
Claim 2
Independent Claim
153 words
A method for fabricating NPN lateral bipolar transistors on an N type substrate, which comprises the following steps of: (a) implanting P type impurity into a predetermined position of said substrate and driving in, to form a P well in said substrate; (b) implanting N type impurity into predetermined positions in the P well, to form N - expanded collector regions of said NPN transistors; (c) implanting P type impurity into predetermined positions in the P well, to form contact regions of base electrode of said NPN transistors; (d) implanting N type impurity into predetermined positions in the P well and the N - expanded collector regions, to form emitter electrodes and collector electrodes of said NPN transistors respectively; (e) forming a field oxide layer over said NPN transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said NPN transistors.
Claim 3
Independent Claim
127 words
A method for fabricating PNP lateral bipolar transistors on an N type substrate, which comprises the following steps of: (a) implanting P type impurity into predetermined positions in said substrate, to form P - expanded collector regions of said PNP transistors; (b) implanting N type impurity into predetermined positions in said substrate, to form contact regions of base electrode of said PNP transistors; (c) implanting P type impurity into predetermined positions in said substrate and the P - expanded collector regions, to form emitter electrodes and collector electrodes of said PNP transistors respectively; (e) forming a field oxide layer over said PNP transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said PNP transistors.
Claim 4
Independent Claim
127 words
A method for fabricating PNP lateral bipolar transistors on an N type substrate, which comprises the following steps of: (a) implanting P type impurity into predetermined positions in said substrate, to form P - expanded collector regions of said PNP transistors; (b) implanting N type impurity into predetermined positions in said substrate, to form contact regions of base electrode of said PNP transistors; (c) implanting P type impurity into predetermined positions in said substrate and the P - expanded collector regions, to form emitter electrodes and collector electrodes of said PNP transistors respectively; (e) forming a field oxide layer over said PNP transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said PNP transistors.
Claim 5
Independent Claim
153 words
A method for fabricating PNP lateral bipolar transistors on an P type substrate, which comprises the following steps of: (a) implanting N type impurity into a predetermined position of said substrate and driving in, to form a N well in said substrate; (b) implanting P type impurity into predetermined positions in the N well, to form P - expanded collector regions of said PNP transistors; (c) implanting N type impurity into predetermined positions in the N well, to form contact regions of base electrode of said PNP transistors; (d) implanting P type impurity into predetermined positions in the N well and the P - expanded collector regions, to form emitter electrodes and collector electrodes of said PNP transistors respectively; (e) forming a field oxide layer over said PNP transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said PNP transistors.
Claim 6
Independent Claim
153 words
A method for fabricating PNP lateral bipolar transistors on an P type substrate, which comprises the following steps of: (a) implanting N type impurity into a predetermined position of said substrate and driving in, to form a N well in said substrate; (b) implanting P type impurity into predetermined positions in the N well, to form P - expanded collector regions of said PNP transistors; (c) implanting N type impurity into predetermined positions in the N well, to form contact regions of base electrode of said PNP transistors; (d) implanting P type impurity into predetermined positions in the N well and the P - expanded collector regions, to form emitter electrodes and collector electrodes of said PNP transistors respectively; (e) forming a field oxide layer over said PNP transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said PNP transistors.
Claim 7
Independent Claim
128 words
A method for fabricating NPN lateral bipolar transistors on an P type substrate, which comprises the 20 following steps of: (a) implanting N type impurity into predetermined positions in said substrate, to form N - expanded collector regions of said NPN transistors; (b) implanting P type impurity into predetermined positions in said substrate, to form contact regions of base electrode of said NPN transistors; (c) implanting N type impurity into predetermined positions in said substrate and the N - expanded collector regions, to form emitter electrodes and collector electrodes of said NPN transistors respectively; (e) forming a field oxide layer over said NPN transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said NPN transistors.
Claim 8
Independent Claim
128 words
A method for fabricating NPN lateral bipolar transistors on an P type substrate, which comprises the 20 following steps of: (a) implanting N type impurity into predetermined positions in said substrate, to form N - expanded collector regions of said NPN transistors; (b) implanting P type impurity into predetermined positions in said substrate, to form contact regions of base electrode of said NPN transistors; (c) implanting N type impurity into predetermined positions in said substrate and the N - expanded collector regions, to form emitter electrodes and collector electrodes of said NPN transistors respectively; (e) forming a field oxide layer over said NPN transistors; and (e) forming metal contacts at the contact regions of the base electrodes, the collector electrodes, and the emitter electrodes of said NPN transistors.
References Cited (Backward Citations)
US3919005A
Cited
US4064526A
Cited
US4120707A
Cited
US4110126A
Cited
US4956305A
Cited
US4966858A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |