Floating-point arithmetic system having multiple-input addition and subtraction means

Claim 2

A floating-point arithmetic system, which allows arithmetic operations including at least addition and subtraction calculations to be performed with respect to floating-point data indicated in the floating-point representation by separating each of said floating-point data into an exponent and a mantissa, comprising: multiple-input addition and subtraction means for executing addition and subtraction calculations of at least three floating-point data, said multiple-input addition and subtraction means, which enables at least three floating-point data to be input, including shift-amount determining means which compares the respective exponents of said floating-point data in parallel with each other, selects the maximum exponent from said exponents, and determines the amount of shift in the respective mantissas of said floating-point data, based on said maximum exponent, said shift amount determining means including a parallel comparator which compares the respective exponents of said floating-point data in parallel with each other, with respect to the magnitude of said exponents, a sequence-discrimination circuit which selects the maximum exponent in accordance with an output from said parallel comparator, and a parallel-exponent-subtraction circuit which calculates a difference between a value of said selected maximum exponent and a value of each of said exponents of said floating-point data, so as to determine the amount of shift in the respective mantissas of said floating-point data; said multiple-input addition and subtraction means also including mantissa shifting means which shifts the respective mantissas of said floating-point data in accordance with said determined amount of shift and makes an adjustment of digit positions of said mantissas; at least one multiple-input adder-subtractor which executes addition and subtraction for said mantissas output from said mantissa shifting means; and a normalization circuit which normalizes a result of said addition and subtraction obtained by said multiple-input adder-subtractor.

Claim 3

A system as set forth in claim 1, wherein said parallel comparator includes: a parallel comparison circuit which has a plurality of positive number comparators provided corresponding to the number of combinations among said floating-point data that are input to said multiple-input means, said positive number comparators comparing the respective exponents of said two different floating-point data with each other in regard to each of said combinations.

Claim 4

A system as set forth in claim 1, wherein said parallel comparator includes: a parallel comparison circuit which has a plurality of positive number comparators provided corresponding to the number of combinations among said floating-point data that are input to said multiple-input means, said positive number comparators comparing the respective exponents of said two different floating-point data with each other in regard to each of said combinations, and wherein said sequence-discrimination circuit includes: a look up table which outputs a select signal for selecting said maximum exponent in accordance with a result of comparison obtained by each of said positive number comparators.

Claim 5

A system as set forth in claim 1, wherein temporary storage means is provided in at least one of boundaries between said shift-amount determining means, said mantissa shifting means and said multiple-input adder-subtractor, and wherein the whole construction of said multiple-input addition and subtraction means takes a form of pipe-line.

Claim 6

A system as set forth in claim 1, wherein an accumulative addition and subtraction calculation device is constituted by utilizing said multiple-input addition and subtraction means.

Claim 7

A system as set forth in claim 1, wherein the system is realized by combining said multiple-input addition and subtraction means, and at least one multiplier.

Claim 8

A system as set forth in claim 1, wherein the system is realized by combining said multiple-input addition and subtraction means, and at least one divider.

Claim 9

A floating-point arithmetic system, which allows arithmetic operations including at least addition and subtraction calculations to be performed with respect to floating-point data indicated in the floating-point representation by separating each of said floating-point data into an exponent and a mantissa, comprising: multiple-input addition and subtraction means for executing addition and subtraction calculations of at least three floating-point data, said multiple-input addition and subtraction means which enables at least three floating-point data to be input, including shift-amount determining means which compares the respective exponents of said floating-point data in parallel with each other, selects the maximum exponent from said exponents, and determines the amount of shift in the respective mantissas of said floating-point data, based on said maximum exponent, said shift-amount determining means including a parallel comparator which compares the respective exponents of said floating-point data in parallel with each other, with respect to the magnitude of said exponents, a sequence-discrimination circuit which selects the maximum exponent in accordance with an output from said parallel comparator, and a parallel-exponent-subtraction circuit which calculates a difference between a value of said selected maximum exponent and a value of each of said exponents of said floating-point data, so as to determine the amount of shift in the respective mantissas of said floating-point data, wherein said parallel comparator includes a parallel comparision circuit which has a plurality of positive number comparators provided corresponding to the number of combinations among said floating-point data that are input to said multiple-input means, said positive number comparators comparing the respective exponents of said two different floating-point data with each other in regard to each of said combinations, wherein said parallel comparator includes a look up table which outputs a select signal for selecting said maximum exponent in accordance with a result of comparison obtained by each of said positive number comparators; said multiple-input addition and subtraction means also including mantissa shifting means which shifts the respective mantissas of said floating-point data in accordance with said determined amount of shift and makes an adjustment of digit positions of said mantissas, said mantissa shifting means including either one stage of a multiplexer or plural stages of multiplexers which execute a shift operation by the length of a plurality of digits with respect to each of said mantissas of said floating-point data; at least one multiple-input adder-subtractor which executes addition and subtraction for said mantissas output from said mantissa shifting means; and a normalization circuit which normalizes a result of said addition and subtraction obtained by said multiple-input adder-subtractor.

Claim 10

A floating-point arithmetic system, which allows arithmetic operations including at least addition and subtraction calculations to be performed with respect to floating-point data indicated in the floating-point representation by separating each of said floating-point data into an exponent and a mantissa, comprising: multiple-input addition and subtraction means for executing addition and subtraction calculations of at least three floating-point data, said multiple-input addition and subtraction means which enables at least three floating-point data to be input, including shift-amount determining means which compares the respective exponents of said floating-point data in parallel with each other, selects the maximum exponent from said exponents, and determines the amount of shift in the respective mantissas of said floating-point data, based on said maximum exponent, said shift-amount determining means including a parallel comparator which compares the respective exponents of said floating-point data in parallel with each other, with respect to the magnitude of said exponents, a sequence-discrimination circuit which selects the maximum exponent in accordance with an output from said parallel comparator, and a parallel-exponent-subtraction circuit which calculates a difference between a value of said selected maximum exponent and a value of each of said exponents of said floating-point data, so as to determine the amount of shift in the respective mantissas of said floating-point data, wherein said parallel comparator includes a parallel comparision circuit which has a plurality of positive number comparators provided corresponding to the number of combinations among said floating-point data that are input to said multiple-input means, said positive number comparators comparing the respective exponents of said two different floating-point data with each other in regard to each of said combinations, wherein said parallel comparator includes a look up table which outputs a select signal for selecting said maximum exponent in accordance with a result of comparison obtained by each of said positive number comparators; said multiple-input addition and subtraction means also including mantissa shifting means which shifts the respective mantissas of said floating-point data in accordance with said determined amount of shift and makes an adjustment of digit positions of said mantissas, said mantissa shifting means including either one stage of a multiplexer or plural stages of multiplexers which execute a shift operation by the length of a plurality of digits with respect to each of said mantissas of said floating-point data; at least one multiple-input adder-subtractor which executes addition and subtraction for said mantissas output from said mantissa shifting means; and a normalization circuit which normalizes a result of said addition and subtraction obtained by said multiple-input adder-subtractor.

Claim 11

A system as set forth in claim 8, wherein temporary storage means is provided in at least one of boundaries between said shift-amount determining means, said mantissa shifting means and said multiple-input adder-subtractor, and wherein the whole construction of said multiple-input addition and subtraction means takes a form of pipe-line.

Claim 12

A system as set forth in claim 8, wherein an accumulative addition and subtraction calculation device is constituted by utilizing said multiple-input addition and subtraction means.

Claim 13

A system as set forth in claim 8, wherein the system is realized by combining said multiple-input addition and subtraction means, and at least one multiplier.

Claim 14

A system as set forth in claim 8, wherein the system is realized by combining said multiple-input addition and subtraction means, and at least one divider.