Weighted-delay column adder and method of organizing same

Claim 3

A method as described in claim 1, wherein: one or more of the adder chains produces two partial results for the binary addition of the bits at that binary-weight.

Claim 4

A method as described in claim 1, further comprising: combining the partial results of the least significant column having two column results, including any carry-out from the previous column, and the column result(s) of the more significant columns in a fast adder stage to provide a final result of the binary addition.

Claim 5

A method as described in claim 1, wherein: one or more of the adder chains produces only one partial result; and further comprising: applying the carry-out with the longest delay from the previous column to the end of the present adder chain as a second partial result.

Claim 6

A method as described in claim 4, further comprising: combining the partial results of the least significant column having two column results, including any carry-out from the previous column, and the column result(s) of the more significant columns in a fast adder stage to provide a final result of the binary addition.

Claim 13

A method as described in claim 8, wherein: at least one of the columns produces more than one result; and further comprising: providing a final parallel adder stage to combine the final results.

Claim 14

A weighted-delay column adder for adding binary numbers, comprising: an array of adders interconnected in chains in a plurality of columns, each column corresponding to the significance of the bits of binary numbers being added and receiving those bits; a first, least significant column of the array of adders organized such that the least significant column of bits from the binary inputs are applied to the adder chains at points having the most nearly matched delay associated therewith, and organized such that the overall delay associated with the column is minimized, with the first column producing a carry-out from each of its component adders which is passed on to the next more significant column, and also producing a final column result which is taken as the least significant bit of the total addition; successive higher columns of the array of adders, each processing the next higher significant column of bits from the binary inputs and the carry signal(s) from the next less significant column, and organized such that the inputs bits are applied to the chain at points having the most nearly matched delay associated therewith, and that the carry signal(s) from the next less significant column array is (are) applied to the array at points having the most nearly matched delay associated therewith or are least impacted by the delay(s) associated with the carry signal(s) from said next less significant column, with each said successive column of the array of adders producing either one or two end results, one of which is the carry signal having the longest associated delay from the next less significant column, both of which said end results are passed on to a final parallel adder stage, and each of said successive columns of the array of adders also producing carry-out signals from each of said successive column's component adders which are passed on to the next more significant column of the array of adders, until a column is reached where there are no more than a total of two inputs, including carries; and a final column, having no more than two inputs, including carry signals, which inputs are passed directly on to a final parallel adder stage.

Claim 15

A weighted-delay column adder for adding binary numbers, comprising: an array of adders interconnected in chains in a plurality of columns, each column corresponding to the significance of the bits of binary numbers being added and receiving those bits; a first, least significant column of the array of adders organized such that the least significant column of bits from the binary inputs are applied to the adder chains at points having the most nearly matched delay associated therewith, and organized such that the overall delay associated with the column is minimized, with the first column producing a carry-out from each of its component adders which is passed on to the next more significant column, and also producing a final column result which is taken as the least significant bit of the total addition; successive higher columns of the array of adders, each processing the next higher significant column of bits from the binary inputs and the carry signal(s) from the next less significant column, and organized such that the inputs bits are applied to the chain at points having the most nearly matched delay associated therewith, and that the carry signal(s) from the next less significant column array is (are) applied to the array at points having the most nearly matched delay associated therewith or are least impacted by the delay(s) associated with the carry signal(s) from said next less significant column, with each said successive column of the array of adders producing either one or two end results, one of which is the carry signal having the longest associated delay from the next less significant column, both of which said end results are passed on to a final parallel adder stage, and each of said successive columns of the array of adders also producing carry-out signals from each of said successive column's component adders which are passed on to the next more significant column of the array of adders, until a column is reached where there are no more than a total of two inputs, including carries; and a final column, having no more than two inputs, including carry signals, which inputs are passed directly on to a final parallel adder stage.

Claim 16

A weighted-delay column adder, according to claim 10, wherein: all columns, including the final column have only one result bit each; and the end result of the addition appears at the column outputs.

Claim 17

A weighted-delay column adder, according to claim 10, wherein: one or more columns has two end results; and all columns, starting with the least significant column having more than one result bit and continuing on to all higher significant columns, are applied to a parallel adder stage suited to two input addends, such as a ripple-carry adder, the output of which parallel adder is taken as the end result of the addition for all of its associated input columns and where the result of the less significant portion of the addition is taken directly from the less significant columns not connected to the parallel adder.

Claim 18

A weighted-delay column adder for adding binary numbers, comprising: a plurality of adders arranged in columns, from a least significant column to a most significant, each column corresponding to the significance (weight) of the bits of binary numbers being added; a first, least significant column receiving the least significant bits of binary numbers being added, providing a result and providing a carry-out to the next more significant column; subsequent, next more significant columns receiving the corresponding next higher significant bits of the binary numbers being added and the carry-outs from less significant columns, providing a result and providing a carry-out to the next more significant column; and a final, most significant column receiving the most significant bits of the binary numbers being added and the carry-outs from the next less significant column and providing two results; wherein delays are associated with positions along the columns; wherein the carry-outs have delays; and the carry-outs from the columns are provided to the more significant columns at positions closely matching the carry-out delays.

Claim 19

A weighted-delay column adder for adding binary numbers, comprising: a plurality of adders arranged in columns, from a least significant column to a most significant, each column corresponding to the significance (weight) of the bits of binary numbers being added; a first, least significant column receiving the least significant bits of binary numbers being added, providing a result and providing a carry-out to the next more significant column; subsequent, next more significant columns receiving the corresponding next higher significant bits of the binary numbers being added and the carry-outs from less significant columns, providing a result and providing a carry-out to the next more significant column; and a final, most significant column receiving the most significant bits of the binary numbers being added and the carry-outs from the next less significant column and providing two results; wherein delays are associated with positions along the columns; wherein the carry-outs have delays; and the carry-outs from the columns are provided to the more significant columns at positions closely matching the carry-out delays.