Dynamic video display for logic simulation systems

Claim 1

An apparatus for converting static simulated test data, produced for a theoretical logic circuit, into a dynamic video display, wherein said simulated test data includes the logic states corresponding to a response of said theoretical logic circuit for a plurality of input signals to said theoretical logic circuit throughout a given time period, said apparatus comprising: an input means for selecting a plurality of input parameters including at least one of said input signals, a start time and a stop time defining a time interval, said start and stop times occurring during said time period, and a plurality of time segments collectively comprising said time interval; synchronizing means for synchronizing each time segment with a synchronization signal; an analysis means for recursively analyzing said time segments whereby logic states corresponding to each said selected input signal occurring during each said analyzed time segment are identified; a converting means for converting said identified logic states into video signals, said video signals being synchronized with said synchronization signal; and a display means operating in response to said video signals to provide a video representation of said identified logic states in time alignment with said synchronization signal and other of said selected input signals for successive time segments between said start time and said stop time, said successive video representations of said identified logic states thereby constituting a dynamic video representation of said response for said theoretical logic circuit to said selected input signals during said given time period.

Claim 2

An apparatus for converting static simulated test data, produced for a theoretical logic circuit, into a dynamic video display, wherein said simulated test data includes the logic states corresponding to a response of said theoretical logic circuit for a plurality of input signals to said theoretical logic circuit throughout a given time period, said apparatus comprising: an input means for selecting a plurality of input parameters including at least one of said input signals, a start time and a stop time defining a time interval, said start and stop times occurring during said time period, and a plurality of time segments collectively comprising said time interval; synchronizing means for synchronizing each time segment with a synchronization signal; an analysis means for recursively analyzing said time segments whereby logic states corresponding to each said selected input signal occurring during each said analyzed time segment are identified; a converting means for converting said identified logic states into video signals, said video signals being synchronized with said synchronization signal; and a display means operating in response to said video signals to provide a video representation of said identified logic states in time alignment with said synchronization signal and other of said selected input signals for successive time segments between said start time and said stop time, said successive video representations of said identified logic states thereby constituting a dynamic video representation of said response for said theoretical logic circuit to said selected input signals during said given time period.

Claim 11

A method of converting simulated logic circuit data into a dynamic video display, wherein said simulated logic data represents a response of a theoretical logic circuit for a plurality of input signals to said theoretical logic circuit over a given time period, said method comprising the steps of: selecting at least one of said input signals; selecting a time interval, beginning with a starting time and ending with a stop time, contained within said time period; dividing said time interval into a plurality of time segments; synchronizing said time segments to a synchronization signal; recursively analyzing said time segments for identifying logic states corresponding to each said selected input signal occurring during each said analyzed time segment; converting said identified logic states into video signals, said video signals being synchronized with said synchronization signal; and consecutively displaying said video signals, in time alignment with said synchronization signal and other of said selected input signals, on a video screen, producing a dynamic video representation of said response for said theoretical logic circuit to said selected input signals during said given time period.

Claim 12

A method of converting simulated logic circuit data into a dynamic video display, wherein said simulated logic data represents a response of a theoretical logic circuit for a plurality of input signals to said theoretical logic circuit over a given time period, said method comprising the steps of: selecting at least one of said input signals; selecting a time interval, beginning with a starting time and ending with a stop time, contained within said time period; dividing said time interval into a plurality of time segments; synchronizing said time segments to a synchronization signal; recursively analyzing said time segments for identifying logic states corresponding to each said selected input signal occurring during each said analyzed time segment; converting said identified logic states into video signals, said video signals being synchronized with said synchronization signal; and consecutively displaying said video signals, in time alignment with said synchronization signal and other of said selected input signals, on a video screen, producing a dynamic video representation of said response for said theoretical logic circuit to said selected input signals during said given time period.

Claim 22

A method of visually analyzing the operational performance of a theoretical logic circuit, prior to the physical construction of said logic circuit, comprising the steps of: creating a mathematical representation of said logic circuit; selecting input data corresponding to a plurality of test signals desired to test said logic circuit; processing said input data through said mathematical representation to produce output data wherein said output data includes logic states corresponding to a response of said logic circuit for each of said test signals expressed across a given time period; selecting output data, corresponding to at least one of said test signals, to be analyzed; selecting a time interval, beginning with a start time and ending with a stop time, contained within said time period; dividing said time interval into a plurality of time segments; synchronizing each said time segment with a synchronization signal; recursively analyzing said time segments for identifying logic states corresponding to each said selected input signal occurring during each said analyzed time segment; converting said identified logic states into a video image, said video images being synchronized with said synchronization signal; and consecutively displaying the video images, in time alignment with said synchronization signal and other of said selected test signals, on a video display, producing a dynamic video representation of said response for said theoretical logic circuit to said selected input signals during said given time period.

Claim 23

A method of visually analyzing the operational performance of a theoretical logic circuit, prior to the physical construction of said logic circuit, comprising the steps of: creating a mathematical representation of said logic circuit; selecting input data corresponding to a plurality of test signals desired to test said logic circuit; processing said input data through said mathematical representation to produce output data wherein said output data includes logic states corresponding to a response of said logic circuit for each of said test signals expressed across a given time period; selecting output data, corresponding to at least one of said test signals, to be analyzed; selecting a time interval, beginning with a start time and ending with a stop time, contained within said time period; dividing said time interval into a plurality of time segments; synchronizing each said time segment with a synchronization signal; recursively analyzing said time segments for identifying logic states corresponding to each said selected input signal occurring during each said analyzed time segment; converting said identified logic states into a video image, said video images being synchronized with said synchronization signal; and consecutively displaying the video images, in time alignment with said synchronization signal and other of said selected test signals, on a video display, producing a dynamic video representation of said response for said theoretical logic circuit to said selected input signals during said given time period.