Method for determining a frequency/time profile of hits, and device for carrying out the method

Claim 1

A device for determining a frequency/time profile of hits, comprising: a) a control unit comprising a personal computer (PC); b) a multiple time interval analyzer (MTIA) for detection, analysis and processing of hit sequences; and c) a PC interface between the MTIA and the PC, which adapts signals coming from the PC to a form required by the MTIA and which adapts signals coming from the MTIA to a form required by the PC, the MTIA comprising: d) two inputs, a first input being a hit input and a second input being a starting pulse input; e) a clock generator which generates a digital system clock; f) a starting pulse synchronization circuit, having a first input connected to the starting pulse input, and having a second input connected to an output of the clock generator, and which locks the starting pulse present at the starting pulse input to the system clock; g) a start/stop logic, having a first input connected to an output of the starting pulse synchronization circuit, and having a second input connected to the system clock, and which controls opening and closing of a measuring window; h) a time mark counter, having a first input connected to the system clock, and having a second input connected to an output of the start/stop logic, and which counts the pulses of the system clock for as long as the output of the start/stop logic is active, wherein the time mark counter comprises a (K+1)-bit binary counter which, after an opening of the measuring window, counts from 0 to 2 K -1, the (K+1)th bit being connected to the start/stop logic and causes the start/stop logic to close the measuring window; i) a hit synchronization circuit, having a first input connected to the hit input, and having a second input connected to the output of the clock generator, and which locks the hit signal present at the hit input to the system clock; k) an AND gate, having a first input connected to an output of the hit synchronization circuit, and having a second input connected to the output of the start/stop logic, and which logically ANDs the two inputs; l) a time mark register, having a load input connected to an output of the AND gate, and having a data input connected to an output of the time mark counter, and which, following an active edge of the signal present at the load input, reads in the value present at the output of the time mark counter, which time mark register comprises a K-bit register; m) a histogram memory, having an address input connected to an output of the time mark register, and which delivers a content of a storage location addressed by the address input to its data output, the histogram memory comprising a (2 K ×D)-bit RAM, D designating a word length of the data; n) a plus one counter, having a data input connected to the data output of the histogram memory, and which increments the value present at its data input by one and writes this value via its data output to the storage location of the histogram memory addressed by the address output of the time mark register, the plus one counter comprising a binary D-bit counter which can be loaded in parallel o) a hit control logic which selects function blocks in accordance with steps d)-n); and p) a control logic which controls data and address flow from and to the PC interface.

Claim 2

A device for determining a frequency/time profile of hits, comprising: a) a control unit comprising a personal computer (PC); b) a multiple time interval analyzer (MTIA) for detection, analysis and processing of hit sequences; and c) a PC interface between the MTIA and the PC, which adapts signals coming from the PC to a form required by the MTIA and which adapts signals coming from the MTIA to a form required by the PC, the MTIA comprising: d) two inputs, a first input being a hit input and a second input being a starting pulse input; e) a clock generator which generates a digital system clock; f) a starting pulse synchronization circuit, having a first input connected to the starting pulse input, and having a second input connected to an output of the clock generator, and which locks the starting pulse present at the starting pulse input to the system clock; g) a start/stop logic, having a first input connected to an output of the starting pulse synchronization circuit, and having a second input connected to the system clock, and which controls opening and closing of a measuring window; h) a time mark counter, having a first input connected to the system clock, and having a second input connected to an output of the start/stop logic, and which counts the pulses of the system clock for as long as the output of the start/stop logic is active, wherein the time mark counter comprises a (K+1)-bit binary counter which, after an opening of the measuring window, counts from 0 to 2 K -1, the (K+1)th bit being connected to the start/stop logic and causes the start/stop logic to close the measuring window; i) a hit synchronization circuit, having a first input connected to the hit input, and having a second input connected to the output of the clock generator, and which locks the hit signal present at the hit input to the system clock; k) an AND gate, having a first input connected to an output of the hit synchronization circuit, and having a second input connected to the output of the start/stop logic, and which logically ANDs the two inputs; l) a time mark register, having a load input connected to an output of the AND gate, and having a data input connected to an output of the time mark counter, and which, following an active edge of the signal present at the load input, reads in the value present at the output of the time mark counter, which time mark register comprises a K-bit register; m) a histogram memory, having an address input connected to an output of the time mark register, and which delivers a content of a storage location addressed by the address input to its data output, the histogram memory comprising a (2 K ×D)-bit RAM, D designating a word length of the data; n) a plus one counter, having a data input connected to the data output of the histogram memory, and which increments the value present at its data input by one and writes this value via its data output to the storage location of the histogram memory addressed by the address output of the time mark register, the plus one counter comprising a binary D-bit counter which can be loaded in parallel o) a hit control logic which selects function blocks in accordance with steps d)-n); and p) a control logic which controls data and address flow from and to the PC interface.

Claim 4

The device as claimed in either one of claims 1 or 2, wherein as higher temporal resolution is achieved by the fact that several MTIAs are used in parallel, which are clocked with deferred system clocks, the hits being distributed to the various MTIAs by means of a hit distribution unit preceding the MTIAs.