Extremely wide range frequency measurement method

Claim 2

A frequency measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f c ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to a content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; a synchronizer and signal decoder for receiving at least an input signal of unknown frequency (f), synchronizing input signals with said reference clock, and providing a measured clock of measured frequency (f M ), proportional to said unknown frequency (f), according to f M =H·f; a pulse counter for counting, in response to said measured clock; means for calculating a modulus value (N c ) on the basis of a desired sampling time (T s ) and said frequency (f c ) of the reference clock; means for loading said modulus value (N c ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N c ), and reloading said interval timer by said modulus value (N c ), in response to said load signal; a timer storage device coupled to said interval timer, for capturing the content of said interval timer, in response to said measured clock; an additional storage device coupled to said timer storage device, for capturing the content of said timer storage device, in response to said sampling clock; a counter storage device coupled to said pulse counter, for capturing the content of said pulse counter, in response to said sampling clock; means for reading and storing the content of said counter storage device, into a second pregiven storage location (B) in said memory after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of said additional storage device, into a first pregiven storage location (A) in said memory, in response to said interrupt request signal; means for reading and storing the content of said counter storage device, into a third pregiven storage location (C) in said memory, in response to said interupt request signal; means for calculating a pulse difference (N P ) as a difference between the content of said second pregiven storage location (B) and the content of said third pregiven storage location (C) in said memory; means for calculating a time difference (N T ) as a sum of already existing value of time difference (N T ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A) in said memory; means for calculating said measured frequency (f M ) of the measured clock by determining the quotient of said pulse difference (N P ) and said time difference (N T ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing the content of said third pregiven storage location (C) into said second pregiven storage location (B) in said memory, after the calculation of said pulse difference (N P ); and means for calculating said time difference (N T ) as incremented content of said first pregiven storage location (A) in said memory, after the calculation of measured frequency (f M ).

Claim 3

A wide-range frequency measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; a synchronizer and signal decoder for receiving at least an input signal of unknown frequency (f), synchronizing input signals with said reference clock, and providing the measured clock of measured frequency (f M ), proportional to said unknown frequency (f), according to f M =H·f; a pulse counter for counting, in response to said measured clock; means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; a timer storage device coupled to said interval timer, for capturing the content of said interval timer, in response to said measured clock; an additional storage device coupled to said timer storage device, for capturing the content of said timer storage device, in response to said sampling clock; a counter storage device coupled to said pulse counter, for capturing the content of said pulse counter, in response to said sampling clock; means for inializing measured frequency (f M ) to zero, before the start of said interval timer; means for initializing a flag (FINDA) to first predetermined value, before the start of said interval timer; means for reading and storing the content of said counter storage device, into a second pregiven storage location (B) in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of said additional storage device, into a first pregiven storage location (A) in said memory, in response to said interrupt request signal; means for reading and storing the content of said counter storage device, into a third pregiven storage location (C) in said memory, in response to said interrupt request signal; means for calculating a pulse difference (N P ) as a difference between the content of said second pregiven storage location (B) and the content of said third pregiven storage location (C) in said memory; means for comparing said pulse difference (N P ) with zero; means for comparing said flag (FINDA) with said first predetermined value; means for calculating a time difference (N T ), in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to the second predetermined value, wherein said time difference (N T ) is calculated as a sum of already existing value of time difference (N T ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A) in said memory; means for calculating said measured frequency (f M ) of the measured clock, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said second predetermined value, wherein said measured frequency (f M ) of the measured clock is calculated as the quotient of said pulse difference (N P ) and said time difference (N T ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing the content of said third pregiven storage location (C) and into said second pregiven storage location (B) in said memory, in response to said pulse difference (N P ) other than zero; means for calculating said time difference (N T ), in response to said pulse difference (N P ) other than zero, after the calculation of measured frequency (f M ), wherein said time difference (N T ) is calculated as incremented content of said first pregiven storage location (A) in said memory; means for initializing said flag (FINDA) to said second predetermined value, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said first predetermined value; and means for initializing measured frequency (f M ) to zero, and initializing said flag (FINDA) to said first predetermined value, in response to said pulse difference (N P ) equal to zero and said flag (FINDA) equal to said second predetermined value.

Claim 4

A wide-range frequency measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; a synchronizer and signal decoder for receiving at least an input signal of unknown frequency (f), synchronizing input signals with said reference clock, and providing the measured clock of measured frequency (f M ), proportional to said unknown frequency (f), according to f M =H·f; a pulse counter for counting, in response to said measured clock; means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; a timer storage device coupled to said interval timer, for capturing the content of said interval timer, in response to said measured clock; an additional storage device coupled to said timer storage device, for capturing the content of said timer storage device, in response to said sampling clock; a counter storage device coupled to said pulse counter, for capturing the content of said pulse counter, in response to said sampling clock; means for inializing measured frequency (f M ) to zero, before the start of said interval timer; means for initializing a flag (FINDA) to first predetermined value, before the start of said interval timer; means for reading and storing the content of said counter storage device, into a second pregiven storage location (B) in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of said additional storage device, into a first pregiven storage location (A) in said memory, in response to said interrupt request signal; means for reading and storing the content of said counter storage device, into a third pregiven storage location (C) in said memory, in response to said interrupt request signal; means for calculating a pulse difference (N P ) as a difference between the content of said second pregiven storage location (B) and the content of said third pregiven storage location (C) in said memory; means for comparing said pulse difference (N P ) with zero; means for comparing said flag (FINDA) with said first predetermined value; means for calculating a time difference (N T ), in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to the second predetermined value, wherein said time difference (N T ) is calculated as a sum of already existing value of time difference (N T ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A) in said memory; means for calculating said measured frequency (f M ) of the measured clock, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said second predetermined value, wherein said measured frequency (f M ) of the measured clock is calculated as the quotient of said pulse difference (N P ) and said time difference (N T ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing the content of said third pregiven storage location (C) and into said second pregiven storage location (B) in said memory, in response to said pulse difference (N P ) other than zero; means for calculating said time difference (N T ), in response to said pulse difference (N P ) other than zero, after the calculation of measured frequency (f M ), wherein said time difference (N T ) is calculated as incremented content of said first pregiven storage location (A) in said memory; means for initializing said flag (FINDA) to said second predetermined value, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said first predetermined value; and means for initializing measured frequency (f M ) to zero, and initializing said flag (FINDA) to said first predetermined value, in response to said pulse difference (N P ) equal to zero and said flag (FINDA) equal to said second predetermined value.

Claim 5

An extremely wide range frequency measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; a synchronizer and signal decoder for receiving at least an input signal of unknown frequency (f), synchronizing input signals with said reference clock, and providing a measured clock of measured frequency (f M ), proportional to said unknown frequency (f), according to f M =H·f; a pulse counter for counting, in response to said measured clock; means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; a timer storage device coupled to said interval timer, for capturing the content of said interval timer, in response to said measured clock; an additional storage device coupled to said timer storage device, for capturing the content of said timer storage device, in response to said sampling clock; a counter storage device coupled to said pulse counter, for capturing the content of said pulse counter, in response to said sampling clock; means for initializing measured frequency (f M ) to zero, before the start of said interval timer; means for initializing a flag (FINDA) to first predetermined value, before the start of said interval timer; means for reading and storing the content of said counter storage device, into a second pregiven storage location (B) in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of said additional storage device, into a first pregiven storage location (A) in said memory, in response to said interrupt request signal; means for reading and storing the content of said counter storage device, into a third pregiven storage location (C) in said memory, in response to said interrupt request signal; means for calculating a pulse difference (N P ) as a difference between the content of said second pregiven storage location (B) and the content of said third pregiven storage location (C) in said memory; means for comparing said pulse difference (N P ) with zero; means for comparing said flag (FINDA) with said first predetermined value; means for calculating a time difference (N T ), in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to a second predetermined value, wherein said time difference (N T ) is calculated as a sum of already existing value of time difference (N T ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A) in said memory; means for calculating said measured frequency (f M ) of the measured clock, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said second predetermined value, wherein said measured frequency (f M ) of the measured clock is calculated as te quotient of said pulse difference (N P ) and said time difference (N T ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing the content of said third pregiven storage location (C) and into said second pregiven storage location (B) in said memory, in response to said pulse difference (N P ) other than zero; means for calculating said time difference (N T ), in response to said pulse difference (N P ) other than zero, after the calculation of measured frequency (f M ), wherein said time difference (N T ) is calculated as incremented content of said first pregiven storage location (A) in said memory; means for initializing said flag (FINDA) to said second predetermined value, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said first predetermined value; means for calculating said time difference (N T ), in response to said pulse difference (N P ) equal to zero, and said flag (FINDA) equal to said second predetermined value, wherein said time difference (N T ) is calculated as a sum of already existing value of time difference (N T ) and an incremented modulus value (N C ); means for comparing said time difference (N T ) with predetermined maximum time difference (maxN T ), in response to said pulse difference (N P ) equal to zero, and said flag (FINDA) equal to said second predetermined value; and means for initializing measured frequency (f M ) to zero, and initializing said flag (FINDA) to said first predetermined value, in response to said pulse difference (N P ) equal to zero, said flag (FINDA) equal to said second predetermined value, and said time difference (N T ) exceeding said predetermined maximum time difference (maxN T ).

Claim 6

An extremely wide range frequency measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; a synchronizer and signal decoder for receiving at least an input signal of unknown frequency (f), synchronizing input signals with said reference clock, and providing a measured clock of measured frequency (f M ), proportional to said unknown frequency (f), according to f M =H·f; a pulse counter for counting, in response to said measured clock; means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; a timer storage device coupled to said interval timer, for capturing the content of said interval timer, in response to said measured clock; an additional storage device coupled to said timer storage device, for capturing the content of said timer storage device, in response to said sampling clock; a counter storage device coupled to said pulse counter, for capturing the content of said pulse counter, in response to said sampling clock; means for initializing measured frequency (f M ) to zero, before the start of said interval timer; means for initializing a flag (FINDA) to first predetermined value, before the start of said interval timer; means for reading and storing the content of said counter storage device, into a second pregiven storage location (B) in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of said additional storage device, into a first pregiven storage location (A) in said memory, in response to said interrupt request signal; means for reading and storing the content of said counter storage device, into a third pregiven storage location (C) in said memory, in response to said interrupt request signal; means for calculating a pulse difference (N P ) as a difference between the content of said second pregiven storage location (B) and the content of said third pregiven storage location (C) in said memory; means for comparing said pulse difference (N P ) with zero; means for comparing said flag (FINDA) with said first predetermined value; means for calculating a time difference (N T ), in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to a second predetermined value, wherein said time difference (N T ) is calculated as a sum of already existing value of time difference (N T ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A) in said memory; means for calculating said measured frequency (f M ) of the measured clock, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said second predetermined value, wherein said measured frequency (f M ) of the measured clock is calculated as te quotient of said pulse difference (N P ) and said time difference (N T ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing the content of said third pregiven storage location (C) and into said second pregiven storage location (B) in said memory, in response to said pulse difference (N P ) other than zero; means for calculating said time difference (N T ), in response to said pulse difference (N P ) other than zero, after the calculation of measured frequency (f M ), wherein said time difference (N T ) is calculated as incremented content of said first pregiven storage location (A) in said memory; means for initializing said flag (FINDA) to said second predetermined value, in response to said pulse difference (N P ) other than zero, and said flag (FINDA) equal to said first predetermined value; means for calculating said time difference (N T ), in response to said pulse difference (N P ) equal to zero, and said flag (FINDA) equal to said second predetermined value, wherein said time difference (N T ) is calculated as a sum of already existing value of time difference (N T ) and an incremented modulus value (N C ); means for comparing said time difference (N T ) with predetermined maximum time difference (maxN T ), in response to said pulse difference (N P ) equal to zero, and said flag (FINDA) equal to said second predetermined value; and means for initializing measured frequency (f M ) to zero, and initializing said flag (FINDA) to said first predetermined value, in response to said pulse difference (N P ) equal to zero, said flag (FINDA) equal to said second predetermined value, and said time difference (N T ) exceeding said predetermined maximum time difference (maxN T ).

Claim 7

The extremely wide range frequency measurement apparatus according to claim 3, further comprising means for calculating a limit frequency (f P ), in response to said pulse difference (N P ) equal to zero, said flag (FINDA) equal to said second predetermined value, and said time difference (N T ) less than said predetermined maximum time difference (maxN T ), wherein said limit frequency (f P ) is calculated as the quotient of said frequency (f C ) of said reference clock, and said time difference (N T ); means for comparing said limit frequency (f P ) with absolute value of measured frequency (f M ); and means for storing value of said limit frequency (f P ) into said measured frequency (f M ) into said memory, keeping previous sign of said measured frequency (f M ), in response to said limit frequency (f P ) less than said absolute value of measured frequency (f M ).

Claim 8

The frequency measurement apparatus according to claim 11, wherein said synchronizer and signal decoder further comprises another input for second input signal, and means for providing an up/down control signal, in response to first and second input signals; and said pulse counter is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 9

The wide-range frequency measurement apparatus according to claim 2, wherein said synchronizer and signal decoder further comprises another input for second input signal, and means for providing an up/down control signal, in response to first and second input signals; and said pulse counter is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 10

The extremely wide-range frequency measurement apparatus according to claim 3, wherein said synchronizer and signal decoder further comprises another input for second input signal, and means for providing the up/down control signal, in response to first and second input signals; and said pulse counter is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 11

The extremely wide-range frequency measurement apparatus according to claim 4, wherein said synchronizer and signal decoder further comprises another input for second input signal, and means for providing the up/down control signal, in response to first and second input signals; and said pulse counter is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 12

N-frequencies measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to the predetermined content; means for the start and stop of said interval timer; means for providing a load signal in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; N synchronizers and signal decoders, wherein each synchronizer and signal decoder is receiving at least an input signal of unknown frequency (f i ), synchronizing its input signals with said reference clock, and providing measured clock of measured frequency (f Mi ), proportional to said unknown frequency (f i ), according to f Mi =H i ·f i ; N pulse counters (PC 1 , . . . ,PC N ) for counting, wherein each pulse counter (PC i ) is counting in response to said measured clock of measured frequency (f Mi ); means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; N timer storage devices (TS 1 , . . . ,TS N ) coupled to said interval timer, wherein each timer storage device TS i ) is capturing the content of said interval timer, in response to said measured clock of measured frequency (f Mi ); N additional storage devices (AS 1 , . . . ,AS N ) wherein each additional storage device (AS i ) is coupled to said timer storage device (TS i ), for capturing the content of said timer storage device (TS i ), in response to said sampling clock; N counter storage devices (CS 1 , . . . ,CS N ), wherein each counter storage device (CS i ) is coupled to said pulse counter (PC i ), for capturing the content of said pulse counter (PC i ), in response to said sampling clock; means for reading and storing the content of each said counter storage device (CS i ), into a second pregiven storage location (B i ) in group (i) of pregiven storage locations in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of each said additional storage device (AS i ), into a first pregiven storage location (A i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for reading and storing the content of each said counter storage device CS i ), into a third pregiven storage location (C i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for calculating N pulse differences (N P1 , . . . ,N PN ), wherein each pulse difference (N Pi ) is calculated as a difference between the content of said second pregiven storage location (B i ) and the content of said third pregiven storage locations (C i ) in said memory; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ), and a difference between said modulus value (N C ) and the content of said pregiven storage location (A i ) in said memory; means for calculating N measured frequencies (f M1 , . . . ,f MN ) of measured clocks, wherein each measured frequency (f Mi ) of measured clock is calculated by determining the quotient of said pulse difference (N Pi ) of said time difference (N Ti ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing N contents of said third pregiven storage locations (C 1 , . . . ,C N ) into said second pregiven storage locations (B 1 , . . . ,B N ), wherein the content of each said third pregiven storage location (C i ) is stored into said second pregiven storage location (B i ) in said memory, after the calculation of pulse difference (N Pi ); and means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as incremented content of said first pregiven storage location (A i ) in said memory, after the calculation of said measured frequency (f Mi ).

Claim 13

N-frequencies measurement apparatus comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to the predetermined content; means for the start and stop of said interval timer; means for providing a load signal in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; N synchronizers and signal decoders, wherein each synchronizer and signal decoder is receiving at least an input signal of unknown frequency (f i ), synchronizing its input signals with said reference clock, and providing measured clock of measured frequency (f Mi ), proportional to said unknown frequency (f i ), according to f Mi =H i ·f i ; N pulse counters (PC 1 , . . . ,PC N ) for counting, wherein each pulse counter (PC i ) is counting in response to said measured clock of measured frequency (f Mi ); means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; N timer storage devices (TS 1 , . . . ,TS N ) coupled to said interval timer, wherein each timer storage device TS i ) is capturing the content of said interval timer, in response to said measured clock of measured frequency (f Mi ); N additional storage devices (AS 1 , . . . ,AS N ) wherein each additional storage device (AS i ) is coupled to said timer storage device (TS i ), for capturing the content of said timer storage device (TS i ), in response to said sampling clock; N counter storage devices (CS 1 , . . . ,CS N ), wherein each counter storage device (CS i ) is coupled to said pulse counter (PC i ), for capturing the content of said pulse counter (PC i ), in response to said sampling clock; means for reading and storing the content of each said counter storage device (CS i ), into a second pregiven storage location (B i ) in group (i) of pregiven storage locations in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of each said additional storage device (AS i ), into a first pregiven storage location (A i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for reading and storing the content of each said counter storage device CS i ), into a third pregiven storage location (C i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for calculating N pulse differences (N P1 , . . . ,N PN ), wherein each pulse difference (N Pi ) is calculated as a difference between the content of said second pregiven storage location (B i ) and the content of said third pregiven storage locations (C i ) in said memory; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ), and a difference between said modulus value (N C ) and the content of said pregiven storage location (A i ) in said memory; means for calculating N measured frequencies (f M1 , . . . ,f MN ) of measured clocks, wherein each measured frequency (f Mi ) of measured clock is calculated by determining the quotient of said pulse difference (N Pi ) of said time difference (N Ti ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing N contents of said third pregiven storage locations (C 1 , . . . ,C N ) into said second pregiven storage locations (B 1 , . . . ,B N ), wherein the content of each said third pregiven storage location (C i ) is stored into said second pregiven storage location (B i ) in said memory, after the calculation of pulse difference (N Pi ); and means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as incremented content of said first pregiven storage location (A i ) in said memory, after the calculation of said measured frequency (f Mi ).

Claim 14

A wide-range measurement apparatus for N-frequencies comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; N synchronizers and signal decoders, wherein each synchronizer and signal decoder receiving at least an input signal of unknown frequency (f i ), synchronizing its input signals with said reference clock, and providing measured clock of measured frequency (f Mi ), proportional to said unknown frequency (f i ), according to f Mi =H i ·f i ; N pulse counters (PC 1 , . . . ,PC N ) for counting, wherein each pulse counter (PC i ) is counting in response to said measured clock of measured frequency (f Mi ); means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; N timer storage devices (TS 1 , . . . ,TS N ) coupled to said interval timer, wherein each timer storage device (TS i ) is capturing the content of said interval timer, in response to said measured clock of measured frequency (f Mi ); N additional storage devices (AS 1 , . . . ,AS N ), wherein each additional storage device (AS i ) is coupled to said timer storage device (TS i ), for capturing the content of said timer storage device (TS i ), in response to said sampling clock; N counter storage devices (CS 1 , . . . ,CS N ), wherein each counter storage device (CS i ) is coupled to said pulse counter (PC i ), for capturing the content of said pulse counter (PC i ), in response to said sampling clock; means for initializing N measured frequencies (f M1 , . . . ,f MN ) to zero, before the start of said interval timer; means for initializing N flags (FINDA 1 , . . . ,FINDA N ) to first predetermined value, before the start of said interval timer; means for reading and storing the content of each said counter storage device (CS 1 ), into a second pregiven storage location (B i ) in group (i) of pregiven storage locations in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of each said additional storage device (AS i ), into a first pregiven storage location (A i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for reading and storing the content of each said counter storage device (CS 1 ), into a third pregiven storage location (C i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for calculating N pulse differences (N P1 , . . . ,N PN ), wherein each pulse difference (N Pi ) is calculated as a difference between the content of said second pregiven storage location (B i ) and the content of said third pregiven storage location (C i ) in said memory; means for comparing each pulse difference (N Pi ) with zero; means for comparing each flag (FINDA i ) with said first predetermined value; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to a second predetermined value, wherein each time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A i ) in said memory; means for calculating N measured frequencies (f M1 , . . . ,f MN ) of measured clocks, wherein each measured frequency (f Mi ) of measured clock is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to said second predetermined value, wherein each frequency (f Mi ) of measured clock is calculated by determining the quotient of said pulse difference (N Pi ) and said time difference (N Ti ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing N contents of said third pregiven storage locations (C 1 , . . . ,C N ) into said second pregiven storage locations (B 1 , . . . ,B N ), wherein the content of each said third pregiven storage location (C i ) is stored into said second pregiven storage location (B i ) in said memory, in response to said pulse difference (N Pi ) other than zero; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as incremented content of said first pregiven storage location (A i ) in said memory, in response to said pulse difference (N Pi ) other than zero, after the calculation of frequency (f Mi ); means for initializing each flag (FINDA i ) to said second predetermined value, in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to said first predetermined value; and means for initializing each measured frequency (f Mi ) to zero, and initializing said flag (FINDA i ) to said first predetermined value, in response to said pulse difference (N Pi ) equal to zero and said flag (FINDA i ) equal to said second predetermined value.

Claim 15

A wide-range measurement apparatus for N-frequencies comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; N synchronizers and signal decoders, wherein each synchronizer and signal decoder receiving at least an input signal of unknown frequency (f i ), synchronizing its input signals with said reference clock, and providing measured clock of measured frequency (f Mi ), proportional to said unknown frequency (f i ), according to f Mi =H i ·f i ; N pulse counters (PC 1 , . . . ,PC N ) for counting, wherein each pulse counter (PC i ) is counting in response to said measured clock of measured frequency (f Mi ); means for calculating a modulus value (N C ) on the basis of a desired sampling time (T S ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; N timer storage devices (TS 1 , . . . ,TS N ) coupled to said interval timer, wherein each timer storage device (TS i ) is capturing the content of said interval timer, in response to said measured clock of measured frequency (f Mi ); N additional storage devices (AS 1 , . . . ,AS N ), wherein each additional storage device (AS i ) is coupled to said timer storage device (TS i ), for capturing the content of said timer storage device (TS i ), in response to said sampling clock; N counter storage devices (CS 1 , . . . ,CS N ), wherein each counter storage device (CS i ) is coupled to said pulse counter (PC i ), for capturing the content of said pulse counter (PC i ), in response to said sampling clock; means for initializing N measured frequencies (f M1 , . . . ,f MN ) to zero, before the start of said interval timer; means for initializing N flags (FINDA 1 , . . . ,FINDA N ) to first predetermined value, before the start of said interval timer; means for reading and storing the content of each said counter storage device (CS 1 ), into a second pregiven storage location (B i ) in group (i) of pregiven storage locations in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of each said additional storage device (AS i ), into a first pregiven storage location (A i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for reading and storing the content of each said counter storage device (CS 1 ), into a third pregiven storage location (C i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for calculating N pulse differences (N P1 , . . . ,N PN ), wherein each pulse difference (N Pi ) is calculated as a difference between the content of said second pregiven storage location (B i ) and the content of said third pregiven storage location (C i ) in said memory; means for comparing each pulse difference (N Pi ) with zero; means for comparing each flag (FINDA i ) with said first predetermined value; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to a second predetermined value, wherein each time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A i ) in said memory; means for calculating N measured frequencies (f M1 , . . . ,f MN ) of measured clocks, wherein each measured frequency (f Mi ) of measured clock is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to said second predetermined value, wherein each frequency (f Mi ) of measured clock is calculated by determining the quotient of said pulse difference (N Pi ) and said time difference (N Ti ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing N contents of said third pregiven storage locations (C 1 , . . . ,C N ) into said second pregiven storage locations (B 1 , . . . ,B N ), wherein the content of each said third pregiven storage location (C i ) is stored into said second pregiven storage location (B i ) in said memory, in response to said pulse difference (N Pi ) other than zero; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as incremented content of said first pregiven storage location (A i ) in said memory, in response to said pulse difference (N Pi ) other than zero, after the calculation of frequency (f Mi ); means for initializing each flag (FINDA i ) to said second predetermined value, in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to said first predetermined value; and means for initializing each measured frequency (f Mi ) to zero, and initializing said flag (FINDA i ) to said first predetermined value, in response to said pulse difference (N Pi ) equal to zero and said flag (FINDA i ) equal to said second predetermined value.

Claim 16

An extremely wide range measurement apparatus for N-frequencies comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; N synchronizers and signal decoders, each synchronizer and signal decoder receiving at least an input signal of unknown frequency (f i ), synchronizing its input signals with said reference clock, and providing measured clock of measured frequency (f Mi ), proportional to said unknown frequency (f i ), according to f Mi =H i ·f i ; N pulse counters (PC 1 , . . . ,PC N ) for counting, wherein each pulse counter (PC i ) is counting in response to said measured clock of measured frequency (f Mi ); means for calculating a modulus value (N C ) on the basis of a desired sampling time (T s ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; N timer storage devices (TS 1 , . . . ,TS N ) coupled to said interval timer, wherein each timer storage device (TS i ) is capturing the content of said interval timer, in response to said measured clock of measured frequency (f Mi ); N additional storage devices (AS 1 , . . . ,AS N ), wherein each additional storage device (AS i ) is coupled to said timer storage device (TS i ), for capturing the content of said timer storage device (TS i ), in response to said sampling clock; N counter storage devices (CS 1 , . . . ,CS N ), wherein each counter storage device (CS i ) is coupled to said pulse counter (PC i ), for capturing the content of said pulse counter (PC i ), in response to said sampling clock; means for initializing N measured frequencies (f M1 , . . . ,f MN ) to zero, before the start of said interval timer; means for initializing N flags (FINDA 1 , . . . ,FINDA N ) to first predetermined value, before the start of said interval timer; means for reading and storing the content of each said counter storage device (CS i ), into a second pregiven storage location (B i ) in group (i) of pregiven storage locations in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of each said additional storage device (AS i ), into a first pregiven storage location (A i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for reading and storing the content of each said counter storage device (CS i ), into a third pregiven storage location (C i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for calculating N pulse differences (N P1 , . . . ,N PN ), wherein each pulse difference (N Pi ) is calculated as a difference between the content of said second pregiven storage location (B i ) and the content of said third pregiven storage location (C i ) in said memory; means for comparing each pulse difference (N Pi ) with zero; means for comparing each flag (FINDA i ) with said first predetermined value; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA 1 ) equal to a second predetermined value, wherein each time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A i ) in said memory; means for calculating N measured frequencies (f M1 , . . . ,f MN ) of measured clocks wherein each measured frequency (f Mi ) of measured clock is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to said second predetermined value, wherein each frequency (f Mi ) of measured clock is calculated by determining the quotient of said pulse difference (N Pi ) and said time difference (N Ti ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing N contents of said third pregiven storage locations (C 1 , . . . ,C N ) into said second pregiven storage locations (B 1 , . . . ,B N ), wherein the content of each said third pregiven storage location (C i ) is stored into said second pregiven storage location (B i ) in said memory, in response to said pulse difference (N Pi ) other than zero; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as incremented content of said first pregiven storage location (A i ) in said memory, in response to said pulse difference (N Pi ) other than zero, after the calculation of frequency (f Mi ); means for initializing each flag (FINDA i ) to said second predetermined value, in response to said pulse difference N Pi ) other than zero, and said flag (FINDA i ) equal to said first predetermined value; means for calculating N time differences (N T1 , . . . ,N TN ) wherein each time difference (N Ti ), is calculated in response to said pulse difference (N Pi ) equal to zero, and said flag (FINDA i ) equal to said second predetermined value, wherein said time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ) and an incremented modulus value (N C ); means for comparing each time difference (N Ti ) with predetermined maximum time difference (maxN Ti ), in response to said pulse difference (N Pi ) equal to zero, and said flag (FINDA 1 ) equal to said second predetermined value; and means for initializing each measured frequency (f Mi ) to zero, and initializing said flag (FINDA i ) to said first predetermined value, in response to said pulse difference (N Pi ) equal to zero, said flag (FINDA i ) equal to said second predetermined value, and said time difference (N Ti ) exceeding said predetermined maximum time difference (maxN Ti ).

Claim 17

An extremely wide range measurement apparatus for N-frequencies comprising: a computer having at least an interrupt input; a memory having a plurality of pregiven storage locations; a reference clock of predetermined constant frequency (f C ); an interval timer for counting, in response to said reference clock, and providing a terminal count signal thereto, in response to the content of said interval timer equal to a predetermined content; means for the start and stop of said interval timer; means for providing a load signal, in response to said terminal count signal; means for providing a sampling clock, in response to said terminal count signal; means for providing an interrupt request signal, in response to said terminal count signal, wherein said interrupt request signal is coupled to said interrupt input of said computer; N synchronizers and signal decoders, each synchronizer and signal decoder receiving at least an input signal of unknown frequency (f i ), synchronizing its input signals with said reference clock, and providing measured clock of measured frequency (f Mi ), proportional to said unknown frequency (f i ), according to f Mi =H i ·f i ; N pulse counters (PC 1 , . . . ,PC N ) for counting, wherein each pulse counter (PC i ) is counting in response to said measured clock of measured frequency (f Mi ); means for calculating a modulus value (N C ) on the basis of a desired sampling time (T s ) and said frequency (f C ) of the reference clock; means for loading said modulus value (N C ) into a modulus storage device, before the start of said interval timer; said modulus storage device coupled to said interval timer, for storing said modulus value (N C ), and reloading said interval timer by said modulus value (N C ), in response to said load signal; N timer storage devices (TS 1 , . . . ,TS N ) coupled to said interval timer, wherein each timer storage device (TS i ) is capturing the content of said interval timer, in response to said measured clock of measured frequency (f Mi ); N additional storage devices (AS 1 , . . . ,AS N ), wherein each additional storage device (AS i ) is coupled to said timer storage device (TS i ), for capturing the content of said timer storage device (TS i ), in response to said sampling clock; N counter storage devices (CS 1 , . . . ,CS N ), wherein each counter storage device (CS i ) is coupled to said pulse counter (PC i ), for capturing the content of said pulse counter (PC i ), in response to said sampling clock; means for initializing N measured frequencies (f M1 , . . . ,f MN ) to zero, before the start of said interval timer; means for initializing N flags (FINDA 1 , . . . ,FINDA N ) to first predetermined value, before the start of said interval timer; means for reading and storing the content of each said counter storage device (CS i ), into a second pregiven storage location (B i ) in group (i) of pregiven storage locations in said memory, after the start of said interval timer, and before first interrupt request signal is activated; means for reading and storing the content of each said additional storage device (AS i ), into a first pregiven storage location (A i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for reading and storing the content of each said counter storage device (CS i ), into a third pregiven storage location (C i ) in group (i) of pregiven storage locations in said memory, in response to said interrupt request signal; means for calculating N pulse differences (N P1 , . . . ,N PN ), wherein each pulse difference (N Pi ) is calculated as a difference between the content of said second pregiven storage location (B i ) and the content of said third pregiven storage location (C i ) in said memory; means for comparing each pulse difference (N Pi ) with zero; means for comparing each flag (FINDA i ) with said first predetermined value; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA 1 ) equal to a second predetermined value, wherein each time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ), and a difference between said modulus value (N C ) and the content of said first pregiven storage location (A i ) in said memory; means for calculating N measured frequencies (f M1 , . . . ,f MN ) of measured clocks wherein each measured frequency (f Mi ) of measured clock is calculated in response to said pulse difference (N Pi ) other than zero, and said flag (FINDA i ) equal to said second predetermined value, wherein each frequency (f Mi ) of measured clock is calculated by determining the quotient of said pulse difference (N Pi ) and said time difference (N Ti ), multiplied with said frequency (f C ) of the reference clock; means for reading and storing N contents of said third pregiven storage locations (C 1 , . . . ,C N ) into said second pregiven storage locations (B 1 , . . . ,B N ), wherein the content of each said third pregiven storage location (C i ) is stored into said second pregiven storage location (B i ) in said memory, in response to said pulse difference (N Pi ) other than zero; means for calculating N time differences (N T1 , . . . ,N TN ), wherein each time difference (N Ti ) is calculated as incremented content of said first pregiven storage location (A i ) in said memory, in response to said pulse difference (N Pi ) other than zero, after the calculation of frequency (f Mi ); means for initializing each flag (FINDA i ) to said second predetermined value, in response to said pulse difference N Pi ) other than zero, and said flag (FINDA i ) equal to said first predetermined value; means for calculating N time differences (N T1 , . . . ,N TN ) wherein each time difference (N Ti ), is calculated in response to said pulse difference (N Pi ) equal to zero, and said flag (FINDA i ) equal to said second predetermined value, wherein said time difference (N Ti ) is calculated as a sum of already existing value of time difference (N Ti ) and an incremented modulus value (N C ); means for comparing each time difference (N Ti ) with predetermined maximum time difference (maxN Ti ), in response to said pulse difference (N Pi ) equal to zero, and said flag (FINDA 1 ) equal to said second predetermined value; and means for initializing each measured frequency (f Mi ) to zero, and initializing said flag (FINDA i ) to said first predetermined value, in response to said pulse difference (N Pi ) equal to zero, said flag (FINDA i ) equal to said second predetermined value, and said time difference (N Ti ) exceeding said predetermined maximum time difference (maxN Ti ).

Claim 18

The extremely wide range frequency measurement apparatus according to claim 11, further comprising means for calculating a limit frequency (f Pi ), in response to said pulse difference (N Pi ) equal to zero, said flag (FINDA i ) equal to said second predetermined value, and said time difference (N Ti ) less than said predetermined maximum time difference (maxN Ti ), wherein said limit frequency (f Pi ) is calculated as the quotient of said frequency (f C ) of said reference clock, and said time difference (N Ti ); means for comparing said limit frequency (f Pi ) with absolute value of measured frequency (f Mi ); and means for storing value of said limit frequency (f Pi ) into said measured frequency (f Mi ) in said memory, keeping the previous sign of said measured frequency (f Mi ), in response to said limit frequency (f Pi ) less than said absolute value of measured frequency (f Mi ).

Claim 19

N-frequency measurement apparatus according to claim 9, wherein each said synchronizer and signal decoder further comprises another input for second input signal, and means for providing the up/down control signal, in response to first and second input signals; and each said pulse counter (PC i ) is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 20

The wide-range measurement apparatus for N-frequencies, according to claim 10, wherein each said synchronizer and signal decoder further comprises another input for second input signal, and means for providing the up/down control signal, in response to first and second input signals; and `each said pulse counter (PC i ) is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 21

The extremely wide-range measurement apparatus for N-frequencies, according to claim 11, wherein each said synchronizer and signal decoder further comprises another input for second input signal, and means for providing the up/down control signal, in response to first and second input signals; and each said pulse counter (PC i ) is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.

Claim 22

The extremely wide-range measurement apparatus for N-frequencies, according to claim 12, wherein each said synchronizer and signal decoder further comprises another input for second input signal, and means for providing the up/down control signal, in response to first and second input signals; and each said pulse counter (PC i ) is an up/down counter, wherein up/down direction of counting is controlled by said up/down control signal.